Signal driver circuit having adjustable output voltage for a high logic level output signal
US-2016240230-A1 · Aug 18, 2016 · US
US9647643B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9647643-B2 |
| Application number | US-201615231449-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 8, 2016 |
| Priority date | Feb 4, 2015 |
| Publication date | May 9, 2017 |
| Grant date | May 9, 2017 |
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The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative g ds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.
Opening claim text (preview).
What is claimed is: 1. A communication system comprising: a clock source for providing a clock signal; an ADC module comprising a buffer circuit, wherein the buffer circuit comprises: a first connection node, a first supply node, a third connection node, a first current feedback node; a first transistor coupled to the first supply node and the first connection node, the first transistor being configured to process a first input signal; a second transistor coupled to the fir…
Electricity · mapped topic
Electricity · mapped topic
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