Fabrication method of vertical type semiconductor memory apparatus
US-9196832-B2 · Nov 24, 2015 · US
Resistive memory array and fabricating method thereof
US9368552B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9368552-B2 |
| Application number | US-201314087782-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 22, 2013 |
| Priority date | Nov 22, 2013 |
| Publication date | Jun 14, 2016 |
| Grant date | Jun 14, 2016 |
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Abstract
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A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.
First claim
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What is claimed is: 1. A method of fabricating a resistive memory array, comprising: forming a plurality of insulators and a conductive structure on a first substrate, wherein the insulators are electrically connected to the conductive structure; performing a resistor-forming process to transform the insulators into a plurality of resistors by applying a forming voltage through the conductive structure; polishing the conductive structure to expose a plurality of contact points…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9368552B2 cover?
- A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate h…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H01L27/2463. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).