Selectively compressed microcode

Patent metadata

Field	Value
Publication number	US-9361097-B2
Application number	US-201314088565-A
Country	US
Kind code	B2
Filing date	Nov 25, 2013
Priority date	Oct 18, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A microprocessor includes one or more memories configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed. A method includes receiving from a memory a first N-bit wide microcode word, determining whether or not a predetermined portion of the first N-bit wide microcode word is a predetermined value, if the predetermined portion is not the predetermined value, decompressing the first N-bit wide microcode word to generate an M-bit wide microcode word, and if the predetermined portion is the predetermined value, receiving from the memory a second N-bit wide microcode word and joining portions of the first and second N-bit wide microcode words to generate the M-bit wide microcode word.

First claim

The invention claimed is:

1. A microprocessor, comprising:
one or more memories, configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed;
a decompression unit, configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed;
wherein the one or more memories are configured to provide words in response to an address input, wherein the words include the microcode instructions at least a portion of which are compressed;
wherein the decompression unit is configured to determine whether the words fetched from the one or more memories include a compressed microcode instruction or a first portion of an uncompressed microcode instruction having a second portion included in an adjacent word;
wherein the decompression unit is configured to decompress the compressed microcode instructions into uncompressed microcode instructions and to join the first and second portions of the uncompressed microcode instructions into uncompressed microcode instructions.

2. The microprocessor of claim 1 ,
wherein to determine whether the words fetched from the one or more memories include a compressed microcode instruction or a first portion of an uncompressed microcode instruction, the decompression unit is configured to determine whether or not a predetermined portion of the microcode words is a predetermined value.

3. The microprocessor of claim 2 ,
wherein each of the compressed microcode words is N bits wide;
wherein to decompress the compressed microcode instructions into uncompressed microcode instructions, the decompression unit is configured to decompress the N-bit wide microcode word to generate an M-bit wide microcode word, wherein M and N are integers greater than zero, and M is greater than N.

4. The microprocessor of claim 3 , wherein to decompress the N-bit wide microcode word to generate an M-bit wide microcode word, the decompression unit is configured to:
output unique L-bit values in response to unique values included in a predetermined K bits of the N-bit wide microcode word according to a predetermined mapping, wherein K is an integer greater than zero and less than N and L is an integer greater than zero and less than M; and
pass through the remaining (N-K) bits of the N-bit wide microcode word as the remaining (M-L) bits of the M-bit wide microcode word.

5. The microprocessor of claim 4 , wherein the passed through (N-K) bits comprise an immediate value field of the compressed microcode instruction.

6. The microprocessor of claim 1 , wherein a first of the one or more memories is configured to hold compressed microcode instructions provided by the first of the memories as N-bit wide words, wherein a second of the one or more memories is configured to hold uncompressed microcode instructions provided by the second of the memories as M-bit wide words, wherein M and N are integers greater than zero, and M is greater than N.

7. The microprocessor of claim 6 , wherein the second of the one or more memories is configured to hold uncompressed microcode instructions that comprise one or more patches to the compressed microcode instructions provided by the first of the memories.

8. The microprocessor of claim 1 , further comprising:
a plurality of processing cores, each comprising a microcode memory that is one of the one or more memories configured to hold a portion of the compressed microcode instructions;
an uncore microcode memory, shared by the plurality of processor cores, configured to hold a portion of the compressed microcode instructions.

9. A method for selectively decompressing microcode, the method comprising:
receiving from a memory a first N-bit wide microcode word;
determining whether or not a predetermined portion of the first N-bit wide microcode word is a predetermined value;
if the predetermined portion is not the predetermined value, decompressing the first N-bit wide microcode word to generate an M-bit wide microcode word, wherein M and N are integers greater than zero, and M is greater than N; and
if the predetermined portion is the predetermined value, receiving from the memory a second N-bit wide microcode word and joining portions of the first and second N-bit wide microcode words to generate the M-bit wide microcode word.

10. The method of claim 9 , wherein the predetermined portion of the first N-bit wide microcode word is mutually exclusive with the portion of the first N-bit wide microcode word joined with the second N-bit wide microcode word to generate the M-bit wide microcode word.

11. The method of claim 9 , wherein the second N-bit wide microcode word is located at an adjacent address within the memory to the first N-bit wide microcode word.

12. The method of claim 9 , wherein if the predetermined portion is not the predetermined value, said decompressing the first N-bit wide microcode word to generate the M-bit wide microcode word comprises:
decompressing K bits of the first N-bit wide microcode word and passing through (N-K) bits of the first N-bit wide microcode word, wherein K is an integer greater than zero and N is greater than K.

13. The method of claim 12 , wherein said decompressing K bits of the first N-bit wide microcode word comprises:
outputting unique L-bit values in response to unique values included in a predetermined K bits of the N-bit wide microcode word according to a predetermined mapping, L is an integer greater than zero and less than M.

14. A method for generating selectively compressed microcode, the method comprising:
receiving source code that includes microcode assembly language instructions, wherein a portion of the microcode assembly language instructions are each denoted by a directive in the source code;
for each of the microcode assembly language instructions, generating a single-word compressed binary representation of the instruction if it is not denoted by the directive, and generating a multi-word uncompressed binary representation of the instruction if it is denoted by the directive.

15. The method of claim 14 , wherein each word of the single-word compressed binary representations and of the multi-word uncompressed binary representations are a width of a memory within a microprocessor in which the words will be stored.

16. The method of claim 14 , further comprising:
receiving a mapping that, for each unique microcode instruction of the source code that is not denoted by the directive, maps the unique microcode instruction to a unique compression value, wherein said generating the single-word binary representations is performed based on the mapping.

17. The method of claim 16 , wherein the unique compression value to which the unique microcode instruction is mapped comprises only a subset of bits of the single-word compressed binary representation generated for the microcode assembly language instruction.

18. A method, comprising:
holding microcode instructions in one or more memories, wherein at least a portion of the microcode instructions are compressed;
fetching, from the one or more memories, words in response to an address input, wherein the words include the microcode instructions at least a portion of which are compressed;
decompressing the compressed microcode instructions after being fetched from the one or more memories and before being executed;
wherein said decompressing comprises:
determining whether the words fetched from the one or more memories include a compressed microcode instruction or a first portion of an uncompressed

Assignees

• Via Tech Inc

Inventors

• Henry G Glenn
• Parks Terry
• Bean Brent

Classifications

• G06F9/28 Primary

  Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel · CPC title

• G06F9/26

  Address formation of the next micro-instruction (G06F9/28 takes precedence){; Microprogram storage or retrieval arrangements} · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30178 Primary

  of compressed or encrypted instructions · CPC title

• G06F9/3802

  Instruction prefetching · CPC title