Image processing circuit and semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-9443282-B2
Application number	US-201214365349-A
Country	US
Kind code	B2
Filing date	Nov 30, 2012
Priority date	Dec 15, 2011
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

This image processing circuit performs, with reduced power consumption, pipeline processing of image data. This image processing circuit has an image processing unit which performs pipeline processing of image data having N-bit pixel data. The image processing unit has a pipeline register ( 400 ) having upper bit flip-flop circuits ( 401 ), lower-order bit flip-flop circuits ( 402 ), a comparison circuit ( 403 ) which determines whether the input values and the output values of the upper bit flip-flop circuits ( 401 ) are the same, and a clock gating control circuit ( 404 ) which controls supply of the clock signal such that, when the aforementioned input and output values are the same, the clock signal is not supplied to the upper bit flip-flop circuits ( 401 ). The pipeline register ( 400 ) does not have a circuit for controlling supply of the clock signal to the lower 1-bit flip-flop circuits ( 402 ), and holds pixel data or calculation results during pipeline processing.

First claim

The invention claimed is:

1. An image processing circuit comprising:
an input section that receives, as input, image data having pixel data of N bits (N is an integer equal to or greater than two);
an image processing section that performs pipeline processing with respect to the image data based on a clock signal; and
an output section that outputs data acquired by the pipeline processing, wherein
the image processing section comprises:
a higher-order n-bit register that receives, as input, data of higher-order n-bits among the pixel data having the image data on which the pipeline processing is performed by the image processing section;
a lower-order 1-bit register that receives, as input, lower-order 1-bit data which is different from the data of higher-order n-bits among the pixel data;
a comparison circuit that inputs an input value of the higher-order n-bit register and an output value of the higher-order n-bit register among an input value and an output value for the higher-order n-bit register and the lower-order 1-bit register, and determines whether the input value of the higher-order n-bit register and the output value of the higher-order n-bit register are identical; and
a clock gating control circuit that controls supply of the clock signal to the higher-order n-bit register such that the clock signal is not supplied to the higher-order n-bit register when the comparison circuit determines that the input value and the output value are identical, and
a pipeline register that includes no circuit which controls the supply of the clock signal to the lower-order 1-bit register and holds image data or an operation result in the course of the pipeline processing,

the image processing circuit further comprising:
a correlation level detection section that acquires a correlation level indicating a matching frequency between adjacent pixels of the image from the image data; and
a comparison processing mode control section that stops operation of the comparison circuit in a segment in which the correlation level is low.

2. The image processing circuit according to claim 1 , wherein the correlation level detection section acquires the correlation level, using one frame forming the image or a division area resulting from division of the frame, as a unit.

3. The image processing circuit according to claim 2 , wherein the correlation level detection section diverts the correlation level detected in another frame.

4. An image processing circuit comprising:
an input section that receives, as input, image data having pixel data of N bits (N is an integer equal to or greater than two);
an image processing section that performs pipeline processing with respect to the image data based on a clock signal; and
an output section that outputs data acquired by the pipeline processing, wherein
the image processing section comprises:
a higher-order n-bit register that receives, as input, data of higher-order n-bits among the pixel data having the image data on which the pipeline processing is performed by the image processing section;
a lower-order 1-bit register that receives, as input, lower-order 1-bit data which is different from the data of higher-order n-bits among the pixel data;
a comparison circuit that inputs an input value of the higher-order n-bit register and an output value of the higher-order n-bit register among an input value and an output value for the higher-order n-bit register and the lower-order 1-bit register, and determines whether the input value of the higher-order n-bit register and the output value of the higher-order n-bit register are identical;
a clock gating control circuit that controls supply of the clock signal to the higher-order n-bit register such that the clock signal is not supplied to the higher-order n-bit register when the comparison circuit determines that the input value and the output value are identical; and
a pipeline register that includes no circuit which controls the supply of the clock signal to the lower-order 1-bit register and holds image data or an operation result in the course of the pipeline processing, wherein

the image data includes left-eye image data and right-eye image data of a stereo image, and
the image processing section comprises:
a left-eye image processing section that performs the pipeline processing on the left-eye image data; and
a right-eye image processing section that performs the pipeline processing on the right-eye image data,

the image processing circuit further comprising:
an input timing adjustment circuit that adjusts, for each pixel line, at least one of an input timing of the left-eye image data to the left-eye image processing section and an input timing of the right-eye image data to the right-eye image processing section such that the pipeline processing in the left-eye image processing section and the pipeline processing in the right-eye image processing section are performed on a corresponding pixel pair between the left-eye image and the right-eye image at a same time; and
a comparison processing mode setting section that stops operation of the comparison circuit of at least one of the left-eye image processing section and the right-eye image processing section, and that causes the clock gating control circuit of the one image processing section to use a determination result of the comparison circuit of the other image processing section.

5. The image processing circuit according to claim 1 , further comprising a plurality of the image processing sections provided for respective color components forming pixel data to be processed, wherein pipeline registers included in the plurality of the image processing sections have a different bit range of data to be input to the higher-order n-bit register.

6. A semiconductor integrated circuit comprising the image processing circuit according to claim 1 .

Assignees

• Panasonic Corp
• Panasonic Ip Man Co Ltd

Inventors

• Hoshino Masashi
• Harada Masaaki

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title

• Y02B60/1221

  Cross-Sectional Technologies · mapped topic

• G06F9/28

  Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel · CPC title