Method for forming alignment marks and structure of same

Patent metadata

Field	Value
Publication number	US-9355964-B2
Application number	US-201414203242-A
Country	US
Kind code	B2
Filing date	Mar 10, 2014
Priority date	Mar 10, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

First claim

What is claimed is:

1. A method for forming alignment marks, the method comprising:
providing a substrate;
forming one or more zero layer alignment marks of a first width, the first width being measured in a first plane, the first plane being parallel to a major surface of the substrate; and
simultaneously with the forming the one or more zero layer alignment marks, forming one or more active area alignment marks of a second width, the second width being measured in the first plane, the second width being less than the first width.

2. The method of claim 1 , wherein the one or more active area alignment marks are formed in scribe lines separating individual dies on the substrate, along perimeters of each individual die.

3. The method of claim 1 , wherein the one or more active area alignment marks are formed between adjacent shallow trench isolation (STI) regions, the one or more active area alignment marks having a square-grid pattern.

4. The method of claim 1 , wherein the one or more active area alignment marks have a square-grid pattern, the square-grid pattern having a pitch between about 0.2 μm and about 1 μm.

5. The method of claim 1 , wherein the first width is between about 100 to about 1000 times larger than the second width.

6. The method of claim 1 , wherein the substrate has a pixel region and a frame cell region, and the one or more active area alignment marks are formed in the frame cell region.

7. The method of claim 6 , wherein the pixel region is of a non-shallow trench isolation (non-STI) design.

8. A method for forming alignment marks, the method comprising:
forming a plurality of pixel regions on a substrate, the plurality of pixel regions being a non-shallow trench isolation (non-STI) design;
forming one or more first alignment marks on the substrate, the one or more first alignment marks having a first width, the first width being measured in a first plane, the first plane being parallel to a major surface of the substrate; and
forming one or more second alignment marks on the substrate, the one or more second alignment marks having a second width, the second width being measured in the first plane, the second width being less than the first width.

9. The method of claim 8 , the one or more second alignment marks are formed in a plurality frame cell regions on the substrate.

10. The method of claim 8 , wherein the one or more first alignment marks comprise one or more zero layer alignment marks.

11. The method of claim 8 , wherein the one or more second alignment marks comprise one or more active area alignment marks.

12. The method of claim 8 , wherein the one or more second alignment marks have square-grid patterns, the square-grid patterns having a pitch between about 0.2 μm and about 1 μm.

13. The method of claim 8 , wherein the first width is between about 100 to about 1000 times larger than the second width.

14. The method of claim 8 , wherein the one or more first alignment marks and the one or more second alignment marks are simultaneously formed on the substrate.

15. A method for forming alignment marks, the method comprising:
forming one or more first alignment marks of a first width on a substrate, the first width being measured in a first plane, the first plane being parallel to a major surface of the substrate, the substrate having a plurality of die regions separated by scribe lines, at least one first alignment mark overlapping with at least one die region; and
simultaneously with the forming the one or more first alignment marks, forming one or more second alignment marks of a second width within the scribe lines, the second width being measured in the first plane, the second width being less than the first width.

16. The method of claim 15 , wherein forming the one or more first alignment marks comprises:
patterning the substrate to form a recess in the substrate; and
forming a dielectric material in the recess.

17. The method of claim 16 , wherein a top surface of the dielectric material has a bump above a sidewall of the recess.

18. The method of claim 15 , wherein forming the one or more second alignment marks comprises:
patterning the substrate to form a recess in the substrate; and
filling the recess with a dielectric material.

19. The method of claim 15 , wherein the one or more second alignment marks have a square-grid pattern, the square-grid pattern having a pitch between about 0.2 μm and about 1 μm.

20. The method of claim 15 , wherein the first width is between about 100 to about 1000 times larger than the second width.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chou Cheng-Hsien
• Chen Sheng-Chau
• Chang Chun-Wei
• Hsu Kai-Chun
• Lai Chih-Yu
• Hsu Wei-Cheng
• Tseng Hsiao-Hui
• Chou Shih Pei
• Ting Shyh-Fann
• Hsu Tzu-Hsuan
• Wang Ching-Chun
• Tu Yeur-Luen
• Yaung Dun-Nian

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/501

  for use before dicing · CPC title