Systems and methods for clock distribution in a die-to-die interface

Patent metadata

Field	Value
Publication number	US-9350339-B2
Application number	US-201414335681-A
Country	US
Kind code	B2
Filing date	Jul 18, 2014
Priority date	Jul 18, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

First claim

What is claimed is:

1. A multi-die package comprising:
a first die having a transmit clock tree feeding a first plurality of flip-flops; and
a second die having a receive clock tree feeding a second plurality of flip-flops, wherein the transmit clock tree is configured to forward a clock signal to the receive clock tree;
wherein individual flip-flops on the first die have a bit correspondence to respective individual flip-flops on the second die, each clock tree being unbalanced and configured to provide matched insertion delays for corresponding flip-flops on the first and second die, wherein the individual flip-flops of the first plurality of flip-flops have different insertion delays relative to each other, and wherein the individual flip-flops of the second plurality of flip-flops have different insertion delays relative to each other.

2. The multi-die package of claim 1 , wherein corresponding flip-flops are connected across the die by data routes, wherein the data routes are the same length.

3. The multi-die package of claim 1 , wherein the first plurality of flip-flops and the second plurality of flip-flops are configured to receive a same clock.

4. The multi-die package of claim 1 , wherein the transmit clock tree has non-uniform route lengths, and wherein the receive clock tree has non-uniform route lengths.

5. The multi-die package of claim 1 , wherein the multi-die package further comprises:
a substrate upon which the first and second die are disposed;
a plurality of metal layers configured to provide electrical communication between the first and second die and with external pins of the package; and
dielectric layers grown over the first and second die.

6. The multi-die package of claim 1 , wherein the multi-die package further includes:
an interposer configured to provide electrical communication between the first and second die and with external pins of the package.

7. The multi-die package of claim 1 , wherein an insertion delay for a given flip-flop of the first plurality of flip-flops includes a propagation delay from a time the clock signal rises at a start node of the transmit clock tree to a time the clock rises at the given flip flop.

8. The multi-die package of claim 1 , wherein an insertion delay for a given flip-flop of the second plurality of flip-flops includes a propagation delay from a time the clock signal rises at a start node of the receive clock tree to a time the clock rises at the given flip flop.

9. A method for providing a clock signal at a die-to-die interface, the method comprising:
at a first clock tree at a first die: distributing the clock signal to a first plurality of flip-flops, each of the flip-flops of the first plurality transmitting data to a corresponding receive flip-flop in response to the clock signal; and
forwarding the clock to a second clock tree at a second die;

at the second clock tree, wherein each of the corresponding receive flip-flops is in a second plurality of flip-flops: distributing the clock signal to the second plurality of flip-flops, each of the flip-flops of the second plurality capturing data from a corresponding one of the first plurality of flip-flops in response to the clock signal;
wherein the first clock tree distributes the clock signal with different insertion delays for each of the flip-flops of the first plurality of flip-flops.

10. The method of claim 9 , wherein the second clock tree distributes the clock signal with different insertion delays for each of the receive flip-flops of the second plurality of flip-flops.

11. The method of claim 10 , wherein an insertion delay at a particular one of the first plurality of flip-flops matches an insertion delay at a corresponding one of the second plurality of flip-flops.

12. The method of claim 9 , wherein a given flip-flop of the first plurality of flip-flops and its corresponding flip-flop of the second plurality of flip-flops are associated with a bit.

Assignees

• Qualcomm Inc

Inventors

• Bryan Thomas Clark
• Loke Alvin Leng Sun
• Knol Stephen
• Lynch Gregory Francis
• Wee Tin Tin
• Peterson Luverne Ray
• Li Yue

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title