Integrated WLUF and SOD process

Patent metadata

Field	Value
Publication number	US-9349698-B2
Application number	US-201213534565-A
Country	US
Kind code	B2
Filing date	Jun 27, 2012
Priority date	Jun 27, 2012
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

First claim

What is claimed is:

1. A wafer, comprising
a plurality of semiconductor chips having a major surface;
a plurality of metal contacts positioned directly on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surfaces of each of the metal contacts substantially parallel to the major surface, wherein each of the contact surfaces defines a thickness of the metal contact relative to the major surface, and wherein the thickness of a first metal contact of the plurality of metal contacts is different from the thickness of a second metal contact of the plurality of metal contacts;
an underfill layer directly abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact;
a solder bump formed in electrical contact with the contact surface of the metal contact, the solder bump having substantially vertical sidewalls, and wherein a width of the solder bump is smaller than a width of the contact surface.

2. The wafer of claim 1 , further comprising a photoresist layer abutting the top surface of the underfill layer and forming a cavity, wherein the solder bump is formed at least in part within the cavity.

3. The wafer of claim 1 , wherein the thickness of the underfill layer is approximately equal to the thickness of the metal contact.

4. The wafer of claim 1 , wherein the metal contact is comprised of copper.

5. The wafer of claim 1 , wherein the underfill layer includes a material that includes an Alpha-1 coefficient of thermal expansion of less than 30*10^(−6) per degree Celsius below a glass transition temperature of the underfill layer.

6. The wafer of claim 1 , wherein the underfill layer includes a material that includes an Alpha-2 coefficient of thermal expansion of less than 120*10^(−6) per degree Celsius above a glass transition temperature.

7. A chip, comprising:
a substrate; and
a plurality of electrical interconnects, each electrical interconnect comprising:
a first metal contact positioned directly on the substrate and having a side surface and contact surface, the contact surface substantially parallel to the substrate and defining a thickness of the first metal contact relative to the substrate;
an underfill layer directly abutting the substrate and the side surface of the first metal contact, the underfill layer having a top surface substantially parallel to the substrate and defining a thickness of the underfill layer relative to the substrate, the thickness of the underfill layer being not greater than the thickness of the first metal contact;
a second metal contact in electrical contact with the contact surface of the first metal contact the second metal contact having substantially vertical sidewalls, and wherein a width of the second metal contact is smaller than a width of the contact surface; and
a third metal contact positioned directly on the substrate and having a side surface and contact surface, the contact surface substantially parallel to the substrate and defining a thickness of the third metal contact relative to the substrate, wherein the thickness of the first metal contact is different from the thickness of the third metal contact.

8. The chip of claim 7 , wherein the plurality of electrical interconnects has a co-planarity between the first metal contact and the second metal contact of not greater than about five micrometers.

9. The chip of claim 7 , wherein the first metal contact comprises copper and the second metal contact comprises solder.

10. The chip of claim 7 , wherein the underfill layer includes a material that includes an Alpha-1 coefficient of thermal expansion of less than 30*10^(−6) per degree Celsius below a glass transition temperature of the underfill layer.

11. The chip of claim 7 , wherein the underfill layer includes a material that includes an Alpha-2 coefficient of thermal expansion of less than 120*10^(−6) per degree Celsius above a glass transition temperature.

Assignees

• Mahmud Rubayat
• Jayaraman Saikumar
• Muthukumar Sriram
• Intel Corp

Inventors

• Mahmud Rubayat
• Jayaraman Saikumar
• Muthukumar Sriram

Classifications

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/01257

  by reflowing · CPC title

• H10W72/01255

  by using masks · CPC title

• H10W72/01223

  in liquid form, e.g. by dispensing droplets or by screen printing · CPC title