Non-volatile semiconductor device

Patent metadata

Field	Value
Publication number	US-8976602-B2
Application number	US-201313783363-A
Country	US
Kind code	B2
Filing date	Mar 3, 2013
Priority date	Aug 13, 2012
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.

First claim

What is claimed is:

1. A non-volatile semiconductor device comprising:
a plurality of first and second selecting transistors;
a plurality of memory cells stacked above a substrate, and connected in series between the first and second selecting transistors;
a plurality of word lines connected to control gates of the plurality of memory cells;
a first selecting gate line connected to gates of the first selecting transistors and a second selecting gate line connected to gates o…

Assignees

• Toshiba Kk

Inventors

• Shiga Hidehiro
• Shirakawa Masanobu

Classifications

• G11C16/14 Primary

  Physics · mapped topic

• G11C16/3436 Primary

  Physics · mapped topic

• H01L27/11573

  Electricity · mapped topic

• G11C16/08

  Physics · mapped topic

• G11C16/3445

  Physics · mapped topic