Nonvolatile memory device, programming method thereof and memory system including the same

US8929145B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8929145-B2
Application numberUS-201314043256-A
CountryUS
Kind codeB2
Filing dateOct 1, 2013
Priority dateFeb 18, 2010
Publication dateJan 6, 2015
Grant dateJan 6, 2015

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Abstract

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Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.

First claim

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What is claimed is: 1. A programming method of a nonvolatile memory device including a substrate and a plurality of strings arranged in rows and columns on the substrate, each string including a plurality of memory cells stacked in a direction vertical to a surface of the substrate and at least first and second string selection transistors stacked in the direction vertical to the surface of the substrate on the plurality of memory cells, first string selection transistors of each r…

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What does patent US8929145B2 cover?
Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell …
Who is the assignee on this patent?
Lee Changhyun, Han Jinman, Kim Doogon, and 3 more
What technology area does this patent fall under?
Primary CPC classification G11C16/107. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).