Semiconductor memory device and method of controlling the same

Patent metadata

Field	Value
Publication number	US-9349446-B2
Application number	US-201514593254-A
Country	US
Kind code	B2
Filing date	Jan 9, 2015
Priority date	Sep 4, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A plurality of word lines extend in a first direction and are disposed in a second direction and a third direction. A plurality of bit lines extend in the third direction and are disposed in the first direction and the second direction. A global bit line is coupled in common to the plurality of bit lines. A selection elements is disposed between the bit line and the global bit line. A control circuit is able to perform respective operations of reading, writing, and deletion on the storage element. A resistive element is disposed on the global bit line side with respect to the selection element. The resistive element adjusts a magnitude of a voltage to be applied to the selection element according to a magnitude of a current flowing through the selection element.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a plurality of word lines that extend in a first direction, the plurality of word lines being disposed in a second direction and a third direction by respective predetermined distances, the second direction intersecting the first direction, the third direction intersecting the first direction and the second direction;
a plurality of bit lines that extend in the third direction, the plurality of bit lines being disposed in the first direction and the second direction by respective predetermined distances;
a variable resistance layer disposed between the word line and the bit line, the variable resistance layer functioning as a storage element;
a global bit line coupled in common to the plurality of bit lines;
a selection element disposed between the bit line and the global bit line;
a control circuit able to perform respective operations of reading, writing, and deletion on the storage element; and
a resistive element disposed on the global bit line side with respect to the selection element, the resistive element having a function to adjust a magnitude of a voltage to be applied to the selection element according to a magnitude of a current flowing through the selection element.

2. The semiconductor memory device according to claim 1 , wherein
the resistive element is a variable resistor.

3. A semiconductor memory device, comprising:
a plurality of word lines that extend in a first direction, the plurality of word lines being disposed in a second direction and a third direction by respective predetermined distances, the second direction intersecting the first direction, the third direction intersecting the first direction and the second direction;
a plurality of bit lines that extend in the third direction, the plurality of bit lines being disposed in the first direction and the second direction by respective predetermined distances;
a variable resistance layer disposed between the word line and the bit line, the variable resistance layer functioning as a storage element;
a global bit line coupled in common to the plurality of bit lines;
a selection element disposed between the bit line and the global bit line;
a control circuit able to perform respective operations of reading, writing, and deletion on the storage element; and
a resistive element disposed on the word line side with respect to the selection element, the resistive element having a function to adjust a magnitude of a voltage to be applied to the selection element according to a magnitude of a current flowing through the selection element.

4. The semiconductor memory device according to claim 3 , wherein
the resistive element is a variable resistor.

5. The semiconductor memory device according to claim 4 , wherein
the plurality of word lines are bundled to a comb-shaped wiring pattern, the wiring pattern being opposed to the first direction, and
the resistive element is a word line driving circuit coupled to the comb-shaped wiring pattern.

6. The semiconductor memory device according to claim 5 , wherein
the word line driving circuit includes a first conductive type first transistor and a second conductive type second transistor, the first transistor being coupled to a first power supply, the second transistor being coupled to a second power supply,
the comb-shaped wiring pattern in the word line is coupled to a node to which an output terminal of the first transistor and an output terminal of the second transistor are coupled, and
the control circuit is able to apply different voltages to respective control terminal of the first transistor and control terminal of the second transistor.

7. A control method of a semiconductor memory device, wherein
the semiconductor memory device includes:
a plurality of word lines that extend in a first direction, the plurality of word lines being disposed in a second direction and a third direction by respective predetermined distances, the second direction intersecting the first direction, the third direction intersecting the first direction and the second direction;
a plurality of bit lines that extend in the third direction, the plurality of bit lines being disposed in the first direction and the second direction by respective predetermined distances;
a variable resistance layer disposed between the word line and the bit line, the variable resistance layer functioning as a storage element;
a global bit line coupled in common to the plurality of bit lines;
a selection element disposed between the bit line and the global bit line;
a control circuit able to perform respective operations of reading, writing, and deletion on the storage element; and
a resistive element disposed on the global bit line side with respect to the selection element, the resistive element having a function to adjust a magnitude of a voltage to be applied to the selection element according to a magnitude of a current flowing through the selection element, wherein

the control method comprises adjusting a resistance value of the variable resistive element according to a length of the global bit line between the selection element corresponding to the selected storage element and the global bit line driving circuit.

Assignees

• Toshiba Kk

Inventors

• Murooka Kenichi

Classifications

• G11C13/0002 Primary

  using resistive RAM [RRAM] elements · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/003

  Cell access · CPC title