Arithmetic operation in a data processing system

Patent metadata

Field	Value
Publication number	US-9348796-B2
Application number	US-201314031854-A
Country	US
Kind code	B2
Filing date	Sep 19, 2013
Priority date	Sep 19, 2013
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

First claim

What is claimed is:

1. A data processing unit, comprising:
approximate result computation circuit that iteratively computes an approximate result of an arithmetic operation performed on at least first and second operands each having a respective sign;
supplementary value computation circuitry including two data registers in which at least two supplementary values of the arithmetic operation are computed concurrently with iterative computation of the approximate result;
selection circuitry that selects a final result of the arithmetic operation from among a set of data inputs including the approximate result and the at least two supplementary values depending on a result of a last iteration of iterative computation by the approximate result computation circuit, wherein the selection circuitry receives, as control inputs, operand sign signals representing the signs of the at least first and second operands and selects the final result in response to the operand sign signals.

2. The data processing unit according to claim 1 , wherein the selection circuitry comprises a multiplexing unit.

3. The data processing unit according to claim 1 , wherein the arithmetic operation is an SRT (Sweeney, Robertson, and Tocher) computation process.

4. The data processing unit according to claim 1 , wherein the arithmetic operation is one of a set including a division operation, square-root operation, addition operation, subtraction operation, and a multiplication operation.

5. The data processing unit according to claim 1 , wherein:
the approximate result computation circuit iteratively computes an approximate result Q of the arithmetic operation by accumulating digit values q concatenated to a previous approximate result Q using a given radix r;
the supplementary value computation circuitry computes iteratively the at least two supplementary values of the approximate result, Q−1 and Q−2, by accumulating digit values q−1 and q−2, respectively, concatenated to previous supplementary values Q−1 and Q−2 using the given radix r;
remainder computation circuitry that computes a remainder P of the arithmetic operation concurrently with the supplementary value computation circuitry; and
the selection circuitry selects, as the final result:
a value of Q for the last iteration in response to the remainder P being greater than or equal to zero and Q being greater than or equal to zero;
a value of Q−1 for the last iteration in response to P being less than zero and Q being greater than or equal to zero;
a negation of a value of Q−1 for the last iteration in response to P being greater than or equal to zero and Q being less than zero; and
a negation of a value of Q−2 for the last iteration in response to P being less than zero and Q being less than zero.

6. The data processing unit according to claim 5 , wherein an absolute value of the digit values q is less than the radix r.

7. A computer program product comprising:
a data storage device;
program code stored within the data storage device that, when executed on a computer, causes the computer to perform:
computing iteratively an approximate result of the arithmetic operation performed on at least first and second operands each having a respective sign,
concurrently with the computing iteratively, computing at least two supplementary values of the approximate result of the arithmetic operation, and
selecting a final result of the arithmetic operation from among a set of data inputs including the approximate result and the at least two supplementary values depending on a result of a last iteration of the computing iteratively, wherein the selecting includes selecting the final result in response to operand sign signals representing the signs of the at least first and second operands.

8. The computer program product according to claim 7 , wherein the arithmetic operation is one of a set including a division operation, square-root operation, addition operation, subtraction operation, and a multiplication operation.

9. The computer program product according to claim 7 , wherein:
the iteratively computing the approximate result comprises iteratively computing an approximate result Q of the arithmetic operation by accumulating digit values q concatenated to a previous approximate result Q using a given radix r;
computing at least two supplementary values comprises computing iteratively the at least two supplementary values of the approximate result, Q−1 and Q−2, by accumulating digit values q−1 and q−2, respectively, concatenated to previous supplementary values Q−1 and Q−2 using the given radix r;
the program code further causes the computer to compute, concurrently with the computation of the at least two supplementary values, a remainder value P of the arithmetic operation;
the selecting the final result comprises:
in response to P being greater than or equal to zero and Q being greater than or equal to zero, selecting as the final result a value of Q for the last iteration;
in response to P being less than zero and Q being greater than or equal to zero, selecting as the final result a value of Q−1 for the last iteration;
in response to P being greater than or equal to zero and Q being less than zero, selecting as the final result a negation of a value of Q−1 for the last iteration; and
in response to P being less than zero and Q being less than zero, selecting as the final result a negation of a value of Q−2 for the last iteration.

10. The computer program product according to claim 9 , wherein an absolute value of the digit values q is less than the radix r.

Assignees

• IBM

Inventors

• Kroener Klaus M
• Layer Christophe J
• Mueller Silvia M
• Schelm Kerstin

Classifications

• G06F17/10 Primary

  Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)} · CPC title

• G06F7/535 Primary

  Dividing only · CPC title

• G06F7/5375

  Non restoring calculation, where each digit is either negative, zero or positive, e.g. SRT; · CPC title