Semiconductor device and data processing system selectively operating as one of a big endian or little endian system

Patent metadata

Field	Value
Publication number	US-9336048-B2
Application number	US-201514802836-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Jun 1, 2005
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.

First claim

What is claimed is:

1. A method for data processing in a data processor including an endian setting register, the method comprising:
receiving an endian setting command;
storing the endian setting command in the endian setting register;
loading the endian setting command; and
after the loading, switching an operation mode based on a value of the endian setting command, the operation mode being switchable between a big endian mode and a little endian mode,
wherein the endian setting command comprises a high-order bit portion and a low-order bit portion, and
wherein the high-order bit portion and the low-order bit portion of the endian setting command are identical.

2. The method for data processing according to claim 1 , the data processor further comprising:
an interface circuit configured to receive the endian setting command; and
a data bus configured to transfer the endian setting command from the interface circuit to the endian setting register,
wherein the bit length of each of the high-order bit portion and the low-order bit portion is the same as the width of the data bus.

3. The method for data processing according to claim 2 , wherein the storing comprises:
when the big endian mode is selected, storing the high-order bit portion in the endian setting register and then storing the low-order bit portion in the endian setting register; and
when the little endian mode is selected, storing the low-order bit portion in the endian setting register and then storing the high-order bit portion in the endian setting register.

4. A method for data processing in a data processor including an endian setting register, the method comprising:
receiving an endian setting command and an endian setting address;
storing the endian setting command in the endian setting register corresponding to the endian setting address;
loading the endian setting command; and
after the loading, switching an operation mode based on a value of the endian setting command, the operation mode being switchable between a big endian mode and a little endian mode,
wherein the endian setting command comprises a high-order bit portion and a low-order bit portion,
wherein the endian setting address comprises a high-order bit portion and a low-order bit portion,
wherein the high-order bit portion and the low-order bit portion of the endian setting command are identical, and
wherein the high-order bit portion and the low-order bit portion of the endian setting address are identical.

5. The method for data processing according to claim 4 , the data processor further comprising:
an interface circuit configured to receive the endian setting command and the endian setting address; and
a data bus configured to transfer the endian setting command from the interface circuit to the endian setting register,
wherein the bit length of each of the high-order bit portion and the low-order bit portion of the endian setting command is the same as the width of the data bus of the data processor, and
wherein the bit length of each of the high-order bit portion and the low-order bit portion of the endian setting address is the same as the width of the data bus of the data processor.

6. The method for data processing according to claim 5 , wherein the storing comprises:
when the big endian mode is selected, storing the high-order bit portion in the endian setting register and then storing the low-order bit portion in the endian setting register; and
when the little endian mode is selected, storing the low-order bit portion in the endian setting register and then storing the high-order bit portion in the endian setting register.

Assignees

• Renesas Electronics Corp

Inventors

• Sakamaki Goro
• Azuma Yuri

Classifications

• G06F13/20

  for access to input/output bus · CPC title

• G06F13/4013

  with data re-ordering, e.g. Endian conversion · CPC title

• G06F9/4806 Primary

  Task transfer initiation or dispatching · CPC title

• G06F13/10 Primary

  Program control for peripheral devices (G06F13/14 - G06F13/42 take precedence) · CPC title

• G06F13/102

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title