Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion

Patent metadata

Field	Value
Publication number	US-9372799-B2
Application number	US-201514841956-A
Country	US
Kind code	B2
Filing date	Sep 1, 2015
Priority date	Oct 24, 2012
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

First claim

What is claimed is:

1. A cache coherence method comprising the steps of:
initiating transaction requests from a coherent cache master, each transaction request accompanied by a unique ID, and each initiated transaction request requiring coherent ownership tracking being further accompanied by an acknowledgement expected signal;
transmitting an acknowledge ID signal corresponding to a unique ID upon said coherent cache master taking ownership of a response to a transaction request;
responding to transaction requests by a cache slave;
transmitting a transaction request initiated by said coherent cache master to said cache slave;
transmitting a response to a transaction request received from said cache slave to said coherent cache master;
cease tracking a response to a transaction request if said corresponding transaction request was not accompanied by an acknowledgement expected signal;
continue tracking a response to a transaction request if said corresponding transaction request was accompanied by an acknowledgement expected signal; and
cease tracking a transaction request/response if said corresponding transaction request was accompanied by an acknowledgement expected signal upon receipt of an acknowledge ID signal corresponding to a unique ID from said coherent cache master.

2. The coherent cache method of claim 1 , wherein:
said cache coherent master includes a plurality of coherent cache masters.

3. The coherent cache system of claim 1 , wherein:
said cache slave includes a plurality of cache slaves.

4. The coherent cache system of claim 1 , further comprising the step of:
transmitting said corresponding unique ID to said coherent cache master upon transmission of said response to said transaction request received from said cache slave.

Assignees

• Texas Instruments Inc

Inventors

• Wu Daniel B
• Pierson Matthew D
• Chirca Kai
• Anderson Timothy D

Classifications

• G06F2212/6042

  Allocation of cache space to multiple users or processors · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title