Clock multiplication and distribution

Patent metadata

Field	Value
Publication number	US-9348358-B2
Application number	US-201414256810-A
Country	US
Kind code	B2
Filing date	Apr 18, 2014
Priority date	Apr 18, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A clock multiplication and distribution system includes a first phase-lock-loop circuit, a second phase-lock-loop circuit, and a clock distribution network that electrically couples the first phase-lock-loop circuit and the second phase-lock-loop circuit. The first phase-lock-loop circuit may include a first feedback loop that includes a first integer divider circuit and may be configured to generate a first clock using a reference clock. A frequency of the first clock may be greater than a frequency of the reference clock. The second phase-lock-loop circuit may include a second feedback loop that includes a second integer divider circuit and may be configured to generate a second clock using the first clock. A frequency of the second clock may be greater than the frequency of the first clock.

First claim

What is claimed is:

1. A clock multiplication and distribution system, comprising:
a physical first phase-lock-loop circuit that includes a first feedback loop with a first integer divider circuit, the first phase-lock-loop circuit configured to generate a first clock using a reference clock, wherein a frequency of the first clock is greater than a frequency of the reference clock;
a physical second phase-lock-loop circuit that includes a second feedback loop with a second integer divider circuit, the second phase-lock-loop circuit configured to generate a second clock using the first clock, wherein a frequency of the second clock is greater than the frequency of the first clock, and a bandwidth of the first phase-lock-loop circuit is greater than a bandwidth of the second phase-lock-loop circuit; and
a physical clock distribution network that electrically couples the first phase-lock-loop circuit and the second phase-lock-loop circuit.

2. The clock multiplication and distribution system of claim 1 , wherein the clock distribution network includes one or more clock repeaters between the first phase-lock-loop circuit and the second phase-lock-loop circuit.

3. The clock multiplication and distribution system of claim 1 , wherein the second phase-lock-loop circuit is one of a plurality of secondary stage phase-lock-loop circuits, wherein each of the secondary stage phase-lock-loop circuits includes a secondary stage feedback loop with a secondary stage integer divider circuit and is configured to generate a secondary stage clock using the first clock, and frequencies of the secondary stage clocks are approximately equal and greater than the frequency of the first clock.

4. The clock multiplication and distribution system of claim 1 , wherein a first multiplier value of the first integer divider circuit is greater than a second multiplier value of the second integer divider circuit.

5. The clock multiplication and distribution system of claim 1 , further comprising a control unit configured to adjust one or more parameters of each of the first phase-lock-loop circuit and the second phase-lock-loop circuit based on jitter of the second clock.

6. The clock multiplication and distribution system of claim 5 , wherein the control unit is configured to adjust the one or more parameters of each of the first phase-lock-loop circuit and the second phase-lock-loop circuit until the jitter of the second clock is less than a first particular amount or a change in the jitter of the second clock is less than a second particular amount.

7. The clock multiplication and distribution system of claim 5 , wherein the one or more parameters of the first phase-lock-loop circuit includes one or more of a gain of an oscillator, a gain of a phase detector, a multiplier value of the first integer divider circuit, and a loop filter parameter.

8. The clock multiplication and distribution system of claim 1 , wherein the first phase-lock-loop circuit and the second phase-lock-loop circuit comprise analog phase-lock-loop circuits or all digital phase-lock-loop circuits.

9. The clock multiplication and distribution system of claim 1 , wherein the clock multiplication and distribution system is included in a transceiver, the transceiver comprising:
a reference clock generator configured to generate the reference clock; and
a data port configured to communicate or receive data over a serial link, the data being clocked with the second clock.

10. A method, comprising:
generating, by way of hardware simulation using a computing system, a first clock using a first phase-lock-loop circuit with a first integer divider circuit, the first clock based on a reference clock and the first clock;
generating, by way of hardware simulation using the computing system, a second clock using a second phase-lock-loop circuit with a second integer divider circuit, wherein the second clock is based on the first clock and the second clock, and a bandwidth of the first phase-lock-loop circuit is greater than a bandwidth of the second phase-lock-loop circuit;
obtaining, by way of hardware simulation using the computing system, a measurement of jitter of the second clock; and
in response to the measurement of jitter being more than a particular jitter amount, adjusting, by way of hardware simulation using the computing system, one or more parameters of the first phase-lock-loop circuit to adjust the jitter of the second clock.

11. The method of claim 10 , wherein in response to the measurement of jitter being more than the particular jitter amount, the method further comprising adjusting one or more parameters of the second phase-lock-loop circuit to adjust the jitter of the second clock.

12. The method of claim 10 , wherein the one or more parameters of the first phase-lock-loop circuit includes one or more of a gain of an oscillator, a gain of a phase detector, a multiplier value of the first integer divider circuit, and a loop filter parameter.

13. The method of claim 10 , wherein a first multiplier value of the first integer divider circuit is greater than a second multiplier value of the second integer divider circuit.

14. The method of claim 10 , wherein the measurement of jitter of the second clock is a first measurement of jitter, the method further comprising:
generating a third clock using a third phase-lock-loop circuit with a third integer divider circuit, the third clock based on the first clock and the third clock;
obtaining a second measurement of jitter of the third clock; and
in response to the first measurement of jitter or the second measurement of jitter being more than the particular jitter amount, adjusting one or more of: one or more first parameters of the first phase-lock-loop circuit, one or more second parameters of the second phase-lock-loop circuit, and one or more third parameters of the third phase-lock-loop circuit until both the first measurement of jitter and the second measurement of jitter are less than the particular jitter amount.

15. A clock multiplication and distribution system, comprising:
a physical first phase-lock-loop circuit that includes a first feedback loop with a first integer divider circuit, the first phase-lock-loop circuit configured to generate a first clock using a reference clock, wherein a frequency of the first clock is greater than a frequency of the reference clock;
a physical second phase-lock-loop circuit electrically coupled to the first phase-lock-loop circuit, wherein the second phase-lock-loop circuit includes a second feedback loop with a second integer divider circuit and is configured to generate a second clock using the first clock, wherein a frequency of the second clock is approximately equal or greater than the frequency of the first clock, and a bandwidth of the first phase-lock-loop circuit is greater than a bandwidth of the second phase-lock-loop circuit; and
a physical control unit electrically coupled to the first phase-lock-loop circuit and the second phase-lock-loop circuit, the control unit configured to adjust one or more parameters of the first phase-lock-loop circuit or of the second phase-lock-loop circuit to adjust a jitter of the second clock.

16. The clock multiplication and distribution system of claim 15 , wherein a first multiplier value of the first integer divider circuit is greater than a second multiplier value of the second integer divider circuit.

Assignees

• Fujitsu Ltd

Inventors

• Walker William W
• Thachile Pradip
• Nedovic Nikola

Classifications

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• H03L7/0898

  the source or sink current values being variable (H03L7/0896 takes precedence) · CPC title