Semiconductor package and printed circuit board

Patent metadata

Field	Value
Publication number	US-9345126-B2
Application number	US-201414198718-A
Country	US
Kind code	B2
Filing date	Mar 6, 2014
Priority date	Mar 13, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A substrate of a semiconductor package comprises a conductor pattern which is formed in a surface layer, and is electrically connected to one terminal out of a power terminal and a ground terminal of a semiconductor element. The substrate also comprises in the surface layer a conductor pattern which is arranged while being separated from the conductor pattern, and a conductor pattern which is formed so as to have a wiring width thinner than that of the conductor pattern and connects the conductor pattern with the conductor pattern. The substrate also comprises a conductor pattern which is formed in an inner layer, faces the conductor pattern through a dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.

First claim

What is claimed is:

1. A semiconductor package comprising:
an interposer; and
a semiconductor element mounted on the interposer, wherein
the interposer comprises a plurality of conductor layers comprising:
a first conductor layer having:
a first conductor pattern which is electrically connected to one terminal out of a power terminal and a ground terminal of the semiconductor element;
a second conductor pattern which is arranged while being separated from the first conductor pattern; and
a third conductor pattern which is formed so as to have a wiring width thinner than that of the second conductor pattern, and connects the first conductor pattern with the second conductor pattern; and

a second conductor layer, which is adjacent to the first conductor layer through a first dielectric, having:
a fourth conductor pattern which faces the second conductor pattern through the first dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.

2. The semiconductor package according to claim 1 , wherein
a pattern unit which is formed of the second conductor pattern, the third conductor pattern and the fourth conductor pattern constitutes a series resonant circuit that corresponds to an operating frequency of the semiconductor element.

3. The semiconductor package according to claim 1 , wherein
the second conductor pattern is arranged in a projected region which corresponds to the semiconductor element projected onto the first conductor layer.

4. The semiconductor package according to claim 1 , comprising:
a plurality of pattern units each of which is formed of the second conductor pattern, the third conductor pattern and the fourth conductor pattern, wherein
the pattern units constitute respective series resonant circuits which correspond to frequencies that are different from each other, respectively.

5. The semiconductor package according to claim 1 , wherein
the third conductor pattern is formed into a meander-shape.

6. The semiconductor package according to claim 1 , wherein
the interposer further comprises a third conductor layer which is adjacent to the second conductor layer through a second dielectric, and
the first dielectric has a dielectric constant larger than that of the second dielectric.

7. The semiconductor package according to claim 1 , wherein
the interposer comprises a third conductor layer which is adjacent to the second conductor layer through a second dielectric, and
a space between the first conductor layer and the second conductor layer is narrower than a space between the second conductor layer and the third conductor layer.

Assignees

• Canon Kk

Inventors

• Hoshi Sou
• Yamashita Nobuaki
• Murai Yusuke

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title