Low temperature in-situ doped silicon-based conductor material for memory cell

Patent metadata

Field	Value
Publication number	US-9343668-B2
Application number	US-201313831043-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Mar 14, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Providing for two-terminal memory cell structures and fabrication that can be achieved with a relatively low temperature process(es) is described herein. By way of example, disclosed two-terminal memory cells can be formed at least in part as a continuous deposition, potentially yielding improved efficiency in manufacturing. Furthermore, various embodiments can be compatible with some existing complementary metal oxide semiconductor fabrication processes, reducing or avoiding retooling overhead that might be associated with modifying existing fabrication processes in favor of other two-terminal memory cell fabrication techniques.

First claim

What is claimed is:

1. A memory cell, comprising:
a silicon (Si) stack consisting of a plurality of Si-based layers formed into a resistive switching memory layer that enters a first electrical state in response to application of a first electrical signal to the memory cell and enters a second electrical state in response to application of a second electrical signal to the memory cell, wherein the second electrical signal has a different magnitude or polarity than the first electrical signal, wherein the plurality of Si-based layers comprise at least a first Si or Si derivative layer doped to a first resistance value and a second Si or Si derivative layer doped to a second resistance value different from the first resistance value, wherein the first Si or Si derivative layer and the second Si or Si derivative layer are adjacent layers within the Si stack without an intervening layer; and
a wiring layer comprised of Si or a Si derivative configured to facilitate application of the first electrical signal or the second electrical signal to the memory cell, wherein the wiring layer is formed adjacent to the Si stack.

2. The memory cell of claim 1 , wherein the Si stack or the wiring layer is adjacent to a complementary metal-oxide semiconductor (CMOS) substrate.

3. The memory cell of claim 1 , wherein the Si or the Si derivative of the wiring layer is doped with n-type or p-type dopants to have a target conductivity value selected to facilitate the wiring layer performing as an electrode to the resistive switching memory layer.

4. The memory cell of claim 3 , wherein the target conductivity value is equal to or greater than a conductivity value of the Si stack in at least the first electrical state or the second electrical state.

5. The memory cell of claim 3 , wherein the dopant is selected from at least one of: boron, indium, gallium, phosphorus, arsenic or antimony.

6. The memory cell of claim 3 , wherein the wiring layer is doped in-situ while adjacent to a CMOS substrate or to the Si stack.

7. The memory cell of claim 1 , wherein the wiring layer is formed via a plasma-enhanced chemical vapor deposition (PECVD) process.

8. The memory cell of claim 7 , wherein the wiring layer is formed via the PECVD process at a temperature less than 350 degrees Celsius.

9. The memory cell of claim 7 , wherein the wiring layer is formed via the PECVD process at a temperature less than 290 degrees Celsius.

10. The memory cell of claim 1 , wherein the memory cell is one of a set of such memory cells arranged in a crossbar memory architecture.

11. The memory cell of claim 1 , wherein the Si derivative is a Si Germanium deposited using a low pressure chemical vapor deposition (LPCVD) or a PECVD process.

12. The memory cell of claim 1 , wherein the Si derivative is a Si Germanium doped with at least one selected from the list of: boron, indium, gallium, phosphorus, arsenic or antimony.

13. The memory cell of claim 1 , wherein the Si-based layers are doped using at least one of an n-type dopant or p-type dopant.

14. The memory cell of claim 1 , wherein the wiring layer and Si stack are in direct contact without an intervening interface layer.

15. The memory cell of claim 1 , wherein:
the wiring layer has a resistivity between about 10 milliOhm-centimeters (mOhm-cm) and about 10 Ohm-cm; and
the first Si layer has resistivity between about 10 mOhm-cm and about 10 Ohm-cm, and the second Si layer has resistivity between about 2 mOhm-cm and about 100 mOhm-cm.

16. A crossbar memory array; comprising:
a plurality of memory cells, wherein at least one of the plurality of memory cells is configured to have a silicon (Si) stack consisting of a plurality of Si-based layers formed into a resistive switching memory layer, the Si-based layers formed of Si or a Si derivative that are doped in-situ to respective target resistance values, wherein the resistive switching memory layer enters a first electrical state in response to a first electrical signal and enters a second electrical state in response to a second electrical signal, and further wherein the plurality of memory cells are arranged in an array comprising at least two-dimensions, wherein the plurality of Si-based layers comprise at least a first Si or Si derivative layer doped to a first resistance value and a second Si or Si derivative layer doped to a second resistance value different from the first resistance value, wherein the first Si or Si derivative layer and the second Si or Si derivative layer are adjacent layers without an intervening layer; and
a wiring component configured to facilitate delivery of the first or second electrical signal, wherein the wiring component is comprised of Si and doped in-situ adjacent to a complementary metal-oxide semiconductor (CMOS) substrate.

17. The crossbar memory array of claim 16 , further comprising at least one of:
a second plurality of the memory cells arranged in a third dimension with respect to the plurality of memory cells.

18. The crossbar memory array of claim 16 , wherein the Si of the wiring component is doped with n-type or p-type dopants to have a target conductivity value selected to facilitate the wiring layer performing as an electrode to the resistive switching memory layer.

19. The crossbar memory array of claim 16 , wherein the target conductivity value is equal to or greater than a conductivity value of the resistive switching memory element in at least the first electrical state or the second electrical state.

20. The crossbar memory array of claim 16 , wherein the dopant is selected from at least one of: boron, indium, gallium, phosphorus, arsenic or antimony.

Assignees

• Crossbar Inc

Inventors

• Maxwell Steve
• Narayanan Sundar
• Jo Sung Hyun
• Kumar Tanmay

Classifications

• H01L45/12 Primary

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic

• H01L45/148

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic