Universal solder joints for 3D packaging

Patent metadata

Field	Value
Publication number	US-9343420-B2
Application number	US-201414181616-A
Country	US
Kind code	B2
Filing date	Feb 14, 2014
Priority date	Feb 14, 2014
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Electronic devices including solder bumps embedded in a pre-applied coating of underfill material and/or solder resist are fabricated, thereby improving chip-package interaction reliability. Underfill can be directly applied to a wafer, enabling increased filler loadings. Passages formed in the underfill and/or solder resist coating expose electrically conductive pads or metal pillars. Such passages can be filled with molten solder to form the solder bumps.

First claim

What is claimed is:

1. A method comprising:
obtaining a structure including a wafer and a plurality of metal contact structures including metal pillars mounted to the wafer, each of the metal pillars having a top surface;
depositing a coating comprising underfill material containing filler material on the wafer, thereby encapsulating the metal pillars;
curing the coating on the wafer;
forming a plurality of passages through the coating such that a plurality of portions of the top surface of each metal pillar are exposed, respectively, by a plurality of the passages, and
filling each of the passages with molten solder, the molten solder forming solder structures contacting the exposed portions of the top surfaces of each metal pillar.

2. The method of claim 1 , wherein forming the plurality of passages includes laser drilling through the coating.

3. The method of claim 1 , wherein the height of each metal pillar is at least equal to the height of each solder structure in contact with the top surface thereof, and the underfill material comprises a thermosetting polymer and the filler material includes silica, alumina, graphene, graphene oxide, graphite or boron nitride.

4. The method of claim 3 , wherein each metal pillar has a diameter at least five times greater than the diameters of each of the solder structures in contact with the top surface thereof and a height greater than the heights of each of the solder structures in contact with the top surface thereof.

5. The method of claim 3 , further including forming the passages such that at least ten portions of the top surface of each metal pillar are exposed.

6. The method of claim 3 , wherein the step of depositing the coating includes depositing a first underfill layer containing the filler material and a second underfill layer adjoining the first underfill layer, the second underfill layer having a substantially lower filler material content than the first underfill layer, the plurality of passages being formed through the second underfill layer.

7. The method of claim 1 , further including providing an electronic assembly comprising a plurality of electrically conductive contact pads and electrically connecting one or more of the metal pillars to one or more of the contact pads via the solder structures by reflowing the solder structures within the passages, each electrical connection of one of the metal pillars with one of the contact pads including a plurality of the solder structures.

8. A method comprising:
providing a first electronic device including a plurality of metal pillars;
providing a second electronic device including a plurality of electrically conductive contact pads, one of the first and second electronic devices including a cured coating comprising at least one of underfill material and solder resist, a plurality of passages extending through the coating, and a plurality of solder structures, each of the solder structures filling one of the passages, the heights of the metal pillars being at least equal to the heights of the solder structures;
causing the first electronic device to contact the second electronic device such that the metal pillars are in opposing relation to the electrically conductive pads and a plurality of the solder structures extend between each metal pillar and each electrically conductive pad, and
bonding the first electronic device and the second electronic device by reflowing the solder structures within the passages such that each of the metal pillars is electrically connected to one of the opposing electrically conductive pads by a plurality of the solder structures.

9. The method of claim 8 , wherein each metal pillar has a diameter at least five times greater than the diameters of each of the solder structures electrically connected thereto and a height greater than the heights of each of the solder structures electrically connected thereto.

10. The method of claim 8 , wherein the coating includes an underfill coating layer containing filler material, further including the steps of forming and curing the underfill coating layer on the first electronic device and encapsulating the metal pillars, forming the passages through the underfill coating layer such that some of the passages expose top surfaces of the metal pillars and others of the passages are located between metal pillars, and filling the passages with solder prior to bonding the first and second electronic devices.

11. The method of claim 8 , wherein the coating includes a cured underfill first layer on the first device containing filler material and a second polymer layer adjoining the first layer, the metal pillars extending through the first layer, the plurality of passages extending through the second layer, the solder structures within the passages electrically contacting the metal pillars.

12. The method of claim 8 , further including the steps of forming and curing the coating on the second electronic device, forming the passages extending through the coating to the contact pads, and filling the passages with solder prior to bonding the first and second electronic devices.

Assignees

• Globalfoundries Inc

Inventors

• Erwin Brian M
• Perfecto Eric D
• Polomoff Nicholas A
• Nah Jae-Woong

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07337

  using a polymer adhesive, e.g. an adhesive based on silicone or epoxy · CPC title