Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices

Patent metadata

Field	Value
Publication number	US-9343303-B2
Application number	US-201414484511-A
Country	US
Kind code	B2
Filing date	Sep 12, 2014
Priority date	Mar 20, 2014
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Methods of forming strain-relaxing semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first semiconductor layer that is lattice-matched with the semiconductor substrate is formed on the porous region. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer being a strained layer as formed. The second semiconductor layer is then relaxed.

First claim

What is claimed is:

1. A strain-relaxing method, comprising:
forming a porous region in a surface of a semiconductor substrate;
forming a first semiconductor layer that is lattice matched with the semiconductor substrate on the porous region in the surface of the semiconductor substrate;
forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer being a strained layer as formed; and
relaxing the second semiconductor layer; and
forming a third semiconductor layer directly on the relaxed second semiconductor layer, the third semiconductor layer being a strained layer as formed; and
relaxing the third semiconductor layer,
wherein the second semiconductor layer comprises a first silicon-germanium layer and the third semiconductor layer comprises a second silicon-germanium layer.

2. The method of claim 1 , wherein forming the porous region in the surface of the semiconductor substrate comprises wet etching a top surface of the semiconductor substrate using a wet etchant with an electrical potential applied between the semiconductor substrate and the wet etchant.

3. The method of claim 1 , wherein before the second semiconductor layer is relaxed, the first semiconductor layer is under tensile stress and the second semiconductor layer is under compressive stress.

4. The method of claim 1 , wherein the first semiconductor layer is only weakly bonded to the semiconductor substrate so that the first semiconductor layer may move with respect to the semiconductor substrate when a tensile stress is applied to the first semiconductor layer.

5. The method of claim 1 , wherein the first semiconductor layer is formed directly on the porous region in the surface of the semiconductor substrate, and the second semiconductor layer is formed directly on the first semiconductor layer.

6. The method of claim 1 , wherein the semiconductor substrate comprises a silicon substrate, the first semiconductor layer comprises a silicon layer, the first silicon-germanium layer has a first germanium concentration, and the second silicon-germanium layer has a second germanium concentration that exceeds the first germanium concentration.

7. The method of claim 6 , wherein the second germanium concentration of the second silicon-germanium layer exceeds 75 percent and a threading dislocation density in the second silicon-germanium layer is less than about 1×10 5 /cm 2 .

8. The method of claim 6 , wherein a total thickness of the silicon layer, the first silicon-germanium layer and the second silicon-germanium layer is less than 75 nm.

9. The method of claim 1 , further comprising:
forming a fourth semiconductor layer on the second semiconductor layer opposite the semiconductor substrate; and
forming a semiconductor device at least partly in or on the fourth semiconductor layer.

10. A method of forming a strain-relaxed semiconductor layer, the method comprising:
forming a first semiconductor layer on top of a compliant region of a semiconductor substrate that is lattice-matched with the first semiconductor layer so that the first semiconductor layer is only weakly bonded to the compliant region of the semiconductor substrate and may move laterally on the top surface of the compliant region of the semiconductor substrate;
forming a second semiconductor layer that is lattice-mismatched with the first semiconductor layer on the first semiconductor layer;
performing a relaxation process on the second semiconductor layer that generates threading dislocations in the first semiconductor layer while leaving the second semiconductor layer substantially free of threading dislocations.

11. The method of claim 10 , further comprising:
forming a third semiconductor layer that is lattice-mismatched with the second semiconductor layer directly on the second semiconductor layer; and
performing a relaxation process on the third semiconductor layer that generates threading dislocations in the second semiconductor layer while leaving the third semiconductor layer substantially free of threading dislocations.

12. The method of claim 11 , wherein the first semiconductor layer is under tensile stress prior to relaxation and the second semiconductor layer is under compressive stress prior to relaxation.

13. The method of claim 11 , wherein the compliant region of the semiconductor substrate comprises a porous region in a top surface of a silicon substrate, the first semiconductor layer comprises a silicon layer, the second semiconductor layer comprises a first silicon-germanium layer having a first germanium concentration, and the third semiconductor layer comprises a second silicon-germanium layer having a second germanium concentration that exceeds the first germanium concentration.

14. The method of claim 13 , wherein the second germanium concentration of the second silicon-germanium layer exceeds 75 percent and a threading dislocation density in the second silicon-germanium layer is less than about 1×10 5 /cm 2 .

15. The method of claim 14 , wherein a total thickness of the silicon layer, the first silicon-germanium layer and the second silicon-germanium layer is less than 75 nm.

16. The method of claim 13 , wherein the porous region has a porosity of at least 30%.

17. The method of claim 10 , wherein forming the first semiconductor layer on top of the compliant region of the substrate that is lattice-matched with the first semiconductor layer so that the first semiconductor layer is only weakly bonded to the compliant region of the semiconductor substrate and may move laterally on the top surface of the compliant region of the semiconductor substrate comprises:
forming a porous region in a top surface of a semiconductor substrate and then heating the semiconductor substrate to close at least some of the surface pores while leaving the interior of the porous region porous to convert the a region of the semiconductor substrate into the compliant region of the semiconductor substrate; and then
epitaxially growing the first semiconductor layer on the porous region by chemical vapor deposition.

18. A method of forming a semiconductor device, the method comprising:
forming a porous region in a top surface of a silicon substrate;
forming a silicon layer on a top surface of the porous region in the top surface of the silicon substrate;
forming a first silicon-germanium layer that has a first germanium concentration on a top surface of the silicon layer;
relaxing the first silicon-germanium layer;
forming a second silicon-germanium layer that has a second germanium concentration that is higher than the first germanium concentration directly on a top surface of the relaxed first silicon-germanium layer, the second silicon-germanium layer being a strained layer as formed;
relaxing the second silicon-germanium layer;
forming a semiconductor layer on a top surface of the second silicon-germanium layer; and
forming the semiconductor device at least partly in the semiconductor layer.

19. The method of claim 18 , wherein forming the porous region in the surface of the silicon substrate comprises wet etching the top surface of the silicon substrate using a wet etchant with an electrical potential applied between the silicon substrate and the wet etchant, the method further comprising annealing the silicon substrate to close at least some of the pores in the top surface of the porous region prior to forming the first silicon-germanium layer.

Assignees

• Wang Wei-E
• Rodder Mark Stephen
• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E
• Rodder Mark Stephen

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/613

  of Group IV materials · CPC title

• H10P14/3451

  Structure · CPC title

• H10P14/3411 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3256

  Microstructure · CPC title