Methods and apparatus for SRAM cell structure

Patent metadata

Field	Value
Publication number	US-9342650-B2
Application number	US-201514715112-A
Country	US
Kind code	B2
Filing date	May 18, 2015
Priority date	Mar 30, 2012
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.

First claim

What is claimed is:

1. A method, comprising:
receiving an SRAM circuit design for forming an array of SRAM cells on a semiconductor substrate;
determining whether a double level photolithography process is to be used for second level contacts in the SRAM cells;
based on the determining, selecting a cell layout including a double level patterning process for second level contacts or selecting a cell layout with a single level patterning process for second level contacts for the SRAM cells; and
using the layout selected, forming the array of SRAM cells on the semiconductor substrate.

2. The method of claim 1 , wherein selecting a cell layout further comprises selecting a cell layout with a relaxed line end rule for the second level contacts with a single layer patterning process.

3. The method of claim 1 , wherein the step of forming the array of SRAM cells includes:
forming first contact structures aligned with respective first nodes of the array of SRAM cells;
forming second contact structures vertically stacked over respective first contact structures, wherein the first contact structures and second contact structures combined extend between a first level metallization layer and the respective first nodes of the array; and
forming third contact structures aligned with respective second nodes of the array of SRAM cells, wherein the third contacts structures extend between the first level metallization layer and the respective second nodes of the array.

4. The method of claim 1 , wherein the step of determining whether a double level photolithography process is to be used includes considering the availability of photolithographic tools, a minimum feature size of a process node, costs associated with extra photomasks and lithography steps, and SRAM cell density desired.

5. The method of claim 4 , wherein the process node is selected from 28 nanometers, 22 nanometers, 20 nanometers, and 14 nanometers.

6. The method of claim 1 , wherein the double level patterning process for second level contacts allows for a lesser spacing between adjacent second level contacts than does the single level patterning process for second level contacts.

7. The method of claim 1 , wherein the second level contacts are aligned to respective first level contacts.

8. The method of claim 1 , wherein the step of forming the array of SRAM cells includes forming butted gate contacts to selected nodes of the array of SRAM cells.

9. A method of manufacturing an SRAM cell, comprising:
evaluating an SRAM cell design for to determine whether a double level photolithography process is to be used for second level contacts in the SRAM cells;
if the evaluation results in a determination to use a double level photolithography process, then manufacturing the SRAM cell by forming SRAM cell transistors, forming first contact structures to contact respective first nodes of the SRAM cell transistors using a single pattern single etch process, and forming second contact structures to contact respective first contact structures using a double pattern double etch process; and
if the evaluation results in a determination to not use a double level photolithography process, then manufacturing the SRAM cell by forming SRAM cell transistors, forming first contact structures to contact respective first nodes of the SRAM cell transistors using a single pattern single etch process, and forming second contact structures to contact respective first contact structures using another single pattern single etch process.

10. The method of claim 9 , further comprising: forming a via structure overlying and contacting at least one of the second contact structures.

11. The method of claim 9 , further comprising forming gate contact structures to contact respective second nodes of the SRAM cell transistors, wherein the gate contact structures have respective topmost surfaces substantially planar with respective topmost surfaces of the second contact structures.

12. The method of claim 9 , wherein the step of evaluating considering the availability of photolithographic tools, a minimum feature size of a process node, costs associated with extra photomasks and lithography steps, and SRAM cell density desired.

13. The method of claim 9 , wherein the SRAM cell is selected from a 6T cell, an 8T cell, a 10T cell, and a content addressable memory cell.

14. The method of claim 9 , wherein the second level contacts are aligned to respective first level contacts.

15. The method of claim 9 , wherein the step of manufacturing the SRAM cell includes forming butted gate contacts to selected nodes of the SRAM cell.

16. The method of claim 9 , further comprising forming third contact structures contacting respective second nodes of the SRAM cell transistors, and wherein the first contact structures and second contact structures combined extend between a first level metallization layer and the respective first nodes of the SRAM cell transistors, and wherein the third contacts structures extend between the first level metallization layer and the respective second nodes of the SRAM cell transistors.

17. A method, comprising:
receiving an SRAM circuit design for forming an array of SRAM cells on a semiconductor substrate;
selecting a first contact structure manufacturing process or a second contact structure manufacturing process based upon a spacing requirement; and
forming the array of SRAM cells on the semiconductor substrate using the selected contact structure manufacturing process, wherein the first contact structure manufacturing process is less expensive than the second contact structure manufacturing process and wherein the second contact structure manufacturing process allows a less spacing requirement than the first contact structure manufacturing process.

18. The method of claim 17 , wherein the first contact structure manufacturing process includes (a) forming first contact structures using a single pattern single etch process and forming stacked second contact structures over the first contact structures using a single pattern single etch process, and wherein the second contact structure manufacturing process includes forming first contact structures using a single pattern single etch process and forming stacked second contact structures over the first contact structures using a double pattern double etch process.

19. The method of claim 17 , further comprising forming gate contact structures over selected nodes of the array of SRAM cells.

20. The method of claim 17 , wherein at least one first contact structure and at least one second contact structure are shared between adjacent SRAM cells of the array of SRAM cells.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Liaw Jhon-Jhy

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• H10D89/10

  Integrated device layouts · CPC title