Static random access memory unit cell structure and static random access memory unit cell layout structure

Patent metadata

Field	Value
Publication number	US-9196352-B2
Application number	US-201313776589-A
Country	US
Kind code	B2
Filing date	Feb 25, 2013
Priority date	Feb 25, 2013
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

First claim

What is claimed is:

1. A static random access memory (SRAM) unit cell layout structure, comprising:
a semiconductor substrate comprising a first active area and a second active area parallel to the first active area;
a first gate line passing through a surface of the first active area and a surface of the second active area;
a first slot contact disposed on the first active area and the second active area both on a same side of the first gate line;
a third active area and a…

Assignees

• United Microelectronics Corp

Inventors

• Hung Ching-Wen
• Tsao Po-Chao
• Wang Shu-Ru
• Huang Chia-Wei
• Chen Chieh-Te
• Chang Feng-Yi
• Huang Chih-Sen

Classifications

• H10D89/10

  Electricity · mapped topic

• G11C11/412 Primary

  Physics · mapped topic

• H01L27/1104

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H10B10/12

  Electricity · mapped topic