Testing holders for chip unit and die package

Patent metadata

Field	Value
Publication number	US-9341671-B2
Application number	US-201313830525-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Mar 14, 2013
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

First claim

What is claimed is:

1. A testing holder for a chip unit, comprising:
a holder body containing the chip unit; and
a pressure releasing device formed on the holder body to release an insertion pressure when the chip unit is inserted in the holder body,
wherein the holder body comprises a bottom plate, and
the chip unit includes a bottom surface facing the bottom plate and an opposing top surface on which a test contactor is disposed.

2. The testing holder of claim 1 , wherein the holder body further comprises a surrounding wall, the chip unit is a diced chip of a 3DIC, and the surrounding wall defines an inner space for containing and testing the diced chip.

3. The testing holder of claim 2 , wherein the surrounding wall further has a tilted surface to guide therein an insertion of the diced chip and to avoid an edge scratch on the diced chip, and the diced chip is one selected from a group consisting of a package on package (PoP), a die package and a die without package.

4. The testing holder of claim 3 , wherein the die without package can be stacked on a dummy die to provide an added height.

5. The testing holder of claim 3 , wherein the bottom plate comprises one set of a first set of plural pogo pins and a second set of plural soft spacers for absorbing a contact stress from the insertion.

6. The testing holder of claim 2 , wherein the surrounding wall further has a trench being the pressure releasing device.

7. The testing holder of claim 2 , wherein the bottom plate is a heat conduct plate having a hole being the pressure releasing device.

8. The testing holder of claim 2 , wherein the holder body further comprises a porous metal plate absorbing a stress from the insertion of the chip unit to prevent a warpage of the chip unit, wherein the bottom plate is a heat conduct plate, the porous metal plate is disposed on the heat conduct plate, and the surrounding wall is disposed on the porous metal plate.

9. The testing holder of claim 2 , wherein the holder body has an upper surrounding wall including a first and a second openings with a first size and a lower surrounding wall including a third opening with a second size, the upper surrounding wall and the lower surrounding wall are connected by plural guide pins, the diced chip has a third size and is insertable into the holder body via the first, the second and the third openings, and the first size is equal to the third size to fix the inserted diced chip.

10. The testing holder of claim 2 , wherein the testing holder has an outer dimension kept unchanged and an inner dimension adapted to a size of the diced chip, the test contactor being one selected from a group consisting of a bump, a probing pad, a contactless coil, a hybrid contactless, and a combination thereof, and the diced chip is tested through the test contactor while the diced chip is inserted into the testing holder.

11. A multi site holding frame for plural chip units, comprising: a first holder frame having a plurality of testing holders, each of the plurality of testing holders including: a holder body containing a specific one of the plural chip units; and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body,
wherein the holder body comprises a bottom plate, and
the specific one of the plural chip units includes a bottom surface facing the bottom plate and an opposing top surface on which a test contactor is disposed.

12. The multi site holding frame of claim 11 further comprising a second holder frame, plural frame guiding pins and a multi site probe card having plural probing devices to probe one of a contact and a contactless transmission, wherein the holder body has an upper surrounding wall including a first and a second openings and a lower surrounding wall including a third opening, the upper surrounding wall and the lower surrounding wall are connected by plural guide pins, and the specific one of the plural diced chip units is insertable into the holder body via the first, the second and the third openings.

13. The multi site holding frame of claim 12 , wherein each of the second holder frame and the first holder frame has plural guiding pin holes, the second holder frame is used to contain all of the upper surrounding walls, the first holder frame is used to contain all of the lower surrounding walls, and the second holder frame and the first holder frame are connected by the plural frame guiding pins inserted into the plural guiding pin holes.

14. The multi site holding frame of claim 11 , wherein the holder body has a surrounding wall, and the surrounding wall is disposed on the bottom plate and defines an inner space for containing and testing the specific one of the plural chip units.

15. The multi site holding frame of claim 11 , wherein each of the plurality of testing holders is replaceable, and the first holder frame further comprises an alignment mark for frame positioning, and the first holder frame is reusable.

16. A method for testing a die, comprising: providing a testing holder; inserting the die into the testing holder; and testing the die via the testing holder to determine whether the die is a defective unit,
wherein the testing holder comprises a bottom plate, and
the die includes a bottom surface facing the bottom plate and an opposing top surface on which a test contactor is disposed.

17. The method of claim 16 , wherein the die is a diced chip and the test contactor is one selected from a group consisting of a bump, a pad, a contactless coil, a hybrid contactless, and a combination thereof, and the diced chip is tested through the test contactor.

18. The method of claim 16 , wherein the die is a diced chip subject to a PoP testing, a CoWoS/CoCoS pre-bond testing and a CoCoS post-bond testing to screen out the defective unit.

19. The method of claim 16 , further comprising: providing plural diced chips of a 3DIC, each of the plural diced chips is the die, and a multi site holding frame including a holder frame having plural testing holders, each of which is the testing holder and is used for containing and testing a specific one of the plural diced chips; inserting the plural diced chips into the respective plural testing holders; and testing the plural diced chips via the respective plural testing holders simultaneously to determine whether each of the plural diced chips is a defective unit.

20. The method of claim 19 , wherein the multi site holding frame further comprises a multi site probe card having plural probe cards for probing one of a contact and a contactless transmission, the holder frame further comprises an alignment mark for frame positioning, each of the plural testing holders is replaceable, the holder frame is reusable, each of the plural diced chips includes the test contactor being one selected from a group consisting of a bump, a probing pad, a contactless coil, a hybrid contactless, and a combination thereof, and each of the plural diced chips is tested through the test contactor.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Wang Mill-Jer
• Liu Kuo-Chuan
• Peng Ching-Nen
• Lin Hung-Chih
• Chen Hao

Classifications

• G01R1/0483

  Sockets for unleaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips · CPC title

• G01R31/2875

  related to heating · CPC title

• G01R31/2867 Primary

  Handlers or transport devices, e.g. loaders, carriers, trays · CPC title

• G01R31/318513 Primary

  Test of Multi-Chip-Moduls · CPC title

• G01R1/06722

  Spring-loaded · CPC title