FinFET spacer formation by oriented implantation

Patent metadata

Field	Value
Publication number	US-9337315-B2
Application number	US-201414157851-A
Country	US
Kind code	B2
Filing date	Jan 17, 2014
Priority date	Nov 3, 2009
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

First claim

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows:

1. A finFET formed by a method comprising:
forming at least one fin of semiconductor material of substantially constant width on a substrate;
forming a gate stack across said fin;
conformally depositing sidewall spacer material on surfaces of said fin, gate stack and said substrate;
etching said sidewall spacer material to form sidewall spacers;
performing angled ion impurity implants into said sidewall spacer material on both sides of said fin in a direction substantially parallel to sides of said gate stack to engender etch selectivity between sidewall spacer material on said fin and sidewall spacer material on said gate stack;
etching said sidewall spacer material to remove said sidewall spacer material from said fin selectively to said sidewall spacer material on said gate stack, said etching being subsequent to said angled ion impurity implant and limited to obtain a substantially uniform shape of spacer material remaining as sidewall spacers on said gate stack without over-etching or significantly reducing height or width of said sidewall spacers on said gate stack but sufficient to remove substantially all of said sidewall spacer material from portions of said fin extending beyond said sidewall spacers on said gate stack due to said etch selectivity; and
performing epitaxial growth on substantially an entirety of said sides but not a top of end portions of said fin to effectively thicken source and drain regions of said fin,
wherein said etching step to remove said sidewall spacer material from said fin comprises etching said spacer material deposited in said step of conformally depositing said spacer material using hydrofluoric acid or an etchant which is slightly anisotropic or selective to a first nitride cap on said fin and a second nitride cap of said gate stack, and
wherein said step of performing an angled implantation is performed after said step of etching said spacer material to form sidewall spacers; and
merging portions of fins of at least two fins exposed by said etching step in said step of epitaxial growth.

2. A finFET formed by a method comprising:
forming at least one fin of semiconductor material of substantially constant width on a substrate;
forming a first nitride cap on said fin;
forming a gate stack including a second nitride cap across said fin;
conformally depositing sidewall spacer material on surfaces of said fin, gate stack and said substrate;
etching said sidewall spacer material to form sidewall spacers;
performing angled ion impurity implants into said sidewall spacer material on both sides of said fin in a direction substantially parallel to sides of said gate stack to engender etch selectivity between sidewall spacer material on said fin and sidewall spacer material on said gate stack;
etching said sidewall spacer material to remove said sidewall spacer material from said fin selectively to said sidewall spacer material on said gate stack, said etching being subsequent to said angled ion impurity implant and limited to obtain a substantially uniform shape of spacer material remaining as sidewall spacers on said gate stack without over-etching or significantly reducing height or width of said sidewall spacers on said gate stack but sufficient to remove substantially all of said sidewall spacer material from portions of said fin extending beyond said sidewall spacers on said gate stack;
performing epitaxial growth on substantially an entirety of said sides but not a top of end portions of said fin to effectively thicken source and drain regions of said fin; and
merging portions of fins of at least two finFETs by said epitaxial growth,
wherein said step of performing an angled implantation is performed prior to said etching step to form sidewall spacers, and
wherein said etching step to remove said sidewall spacer material from said fin comprises etching said spacer material deposited in said step of conformally depositing said spacer material using hydrofluoric acid or an etchant which is slightly anisotropic or selective to said first nitride cap on said fin and said second nitride cap of said gate stack.

3. A finFET formed by a method comprising:
forming at least one fin of semiconductor material of substantially constant width on a substrate;
forming a first nitride cap on said fin;
forming a gate stack including a second nitride cap across said fin;
conformally depositing sidewall spacer material on surfaces of said fin, gate stack and said substrate;
etching said sidewall spacer material to form sidewall spacers;
performing angled ion impurity implants into said sidewall spacer material on both sides of said fin in a direction substantially parallel to sides of said gate stack to engender etch selectivity between sidewall spacer material on said fin and sidewall spacer material on said gate stack;
etching said sidewall spacer material to remove said sidewall spacer material from said fin selectively to said sidewall spacer material on said gate stack, said etching being subsequent to said angled ion impurity implant and limited to obtain a substantially uniform shape of spacer material remaining as sidewall spacers on said gate stack without over-etching or significantly reducing height or width of said sidewall spacers on said gate stack but sufficient to remove substantially all of said sidewall spacer material from portions of said fin extending beyond said sidewall spacers on said gate stack due to said etch selectivity;
performing epitaxial growth on substantially an entirety of said sides but not a top of end portions of said fin to effectively thicken source and drain regions of said fin; and
merging source or drain regions of at least two finFETs,
wherein said step of performing an angled implantation is performed prior to said step of performing said step of etching said spacer material to form sidewall spacers and prior to said step etching said spacer material to remove said spacer material from said fins selectively to said spacer material on said gate stack, and
wherein said etching step to remove said sidewall spacer material from said fin comprises etching said spacer material deposited in said step of conformally depositing said spacer material using hydrofluoric acid or an etchant which is slightly anisotropic or selective to said first nitride cap on said fin and said second nitride cap of said gate stack.

4. The finFET of claim 1 , wherein forming at least one fin of semiconductor material comprises:
forming the first nitride cap on said at least one fin.

5. The finFET of claim 4 , wherein said step of etching said sidewall material on said fin selectively to said sidewall material on said gate stack is also selective to said first nitride cap on said fin and said second nitride cap of said gate stack.

6. The finFET of claim 1 wherein said fin is formed by a sidewall image transfer process.

7. The finFET of claim 2 wherein said fin is formed by a sidewall image transfer process.

8. The finFET of claim 3 wherein said fin is formed by a sidewall image transfer process.

9. The finFET of claim 1 , wherein said step of etching said spacer material to form sidewall spacers is performed by a reactive ion etch process.

Assignees

• Globalfoundries Inc

Inventors

• Basker Veeraraghavan S
• Cheng Kangguo
• Doris Bruce B
• Faltermeier Johnathan E

Classifications

• H10P30/222 Primary

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• H10D84/0158

  the components including FinFETs · CPC title