Manufacture of coated copper pillars

US9331040B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9331040-B2
Application numberUS-201314429364-A
CountryUS
Kind codeB2
Filing dateJul 19, 2013
Priority dateSep 19, 2012
Publication dateMay 3, 2016
Grant dateMay 3, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A layer of a first metal which is more noble than copper is deposited onto the entire outer surface of the copper pillar prior to deposition of the second metal layer. The layer of a second metal then has at least a reduced number of undesired pin-holes and serves as a protection layer for the underlying copper pillar.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for manufacture of coated copper pillars on a semiconducting substrate comprising, in this order, the steps of a. providing a semiconducting substrate with an array of copper pillars, the copper pillars having an underbump metallization area comprising a metal or metal alloy less noble than copper, and a solder cap layer attached to the top portion of the copper pillars, b. depositing a first metal layer comprising a metal which is more noble than copper onto the entire outer surface of the copper pillars, and c. depositing a second metal layer selected from the group consisting of tin, tin alloys, silver, and silver alloys by immersion-type plating onto the first metal layer, wherein the metal which is more noble than copper is selected from the group consisting of silver, palladium, platinum, rhodium, ruthenium, gold and alloys thereof with the proviso that silver and silver alloys are not selected as first metal layer if the second metal layer comprises silver or a silver alloy. 2. The method for manufacture of coated copper pillars according to claim 1 wherein the semiconducting substrate is a silicon substrate. 3. The method for manufacture of coated copper pillars according to claim 1 wherein the solder cap layer comprises tin. 4. The method for manufacture of coated copper pillars according to claim 1 wherein the metal which is more noble than copper is palladium. 5. The method for manufacture of coated copper pillars according to claim 1 wherein the second metal layer comprises tin and further comprises silver. 6. The method for manufacture of coated copper pillars according to claim 1 wherein the second metal layer further comprises copper in the form of a copper-tin alloy. 7. A method for manufacture of coated copper pillars on a semiconducting substrate comprising, in this order, the steps of a. providing a semiconducting substrate with an array of copper pillars, the copper pillars having an underbump metallization area comprising a metal or metal alloy less noble than copper, and a solder cap layer attached to the top portion of the copper pillars, b. depositing a first metal layer comprising a metal which is more noble than copper onto the entire outer surface of the copper pillars, and c. depositing a second metal layer selected from the group consisting of tin, tin alloys, silver, and silver alloys by immersion-type plating bath onto the first metal layer, wherein the first metal layer is deposited by immersion-type plating bath. 8. The method for manufacture of coated copper pillars according to claim 7 wherein the immersion-type plating bath comprises a source of metal ions of the metal more noble than copper and at least one acid and/or salt thereof. 9. The method for manufacture of coated copper pillars according to claim 7 wherein the second metal layer is deposited from an aqueous plating bath comprising a source of tin ions, thiourea and/or a derivative thereof, and optionally a source of a second metal. 10. The method for manufacture of coated copper pillars according to claim 9 wherein the second metal layer further comprises copper in the form of a copper-tin alloy. 11. The method for manufacture of coated copper pillars according to claim 7 wherein the metal which is more noble than copper is selected from the group consisting of silver, palladium, platinum, rhodium, ruthenium, gold and alloys thereof with the proviso that silver and silver alloys are not selected as first metal layer if the second metal layer comprises silver or a silver alloy. 12. The method for manufacture of coated copper pillars according to claim 7 wherein the metal which is more noble than copper is palladium. 13. The method for manufacture of coated copper pillars according to claim 7 wherein the solder cap layer comprises tin. 14. The method for manufacture of coated copper pillars according to claim 7 wherein the second metal layer comprises tin and further comprises silver. 15. A method for manufacture of coated copper pillars on a semiconducting substrate comprising, in this order, the steps of a. providing a semiconducting substrate with an array of copper pillars, the copper pillars having an underbump metallization area comprising a metal or metal alloy less noble than copper, and a solder cap layer attached to the top portion of the copper pillars, b. depositing a first metal layer comprising a metal which is more noble than copper onto the entire outer surface of the copper pillars, and c. depositing a second metal layer selected from the group consisting of tin, tin alloys, silver, and silver alloys by immersion-type plating onto the first metal layer, wherein the second metal layer is tin or a tin alloy. 16. The method for manufacture of coated copper pillars according to claim 15 wherein the metal which is more noble than copper is palladium. 17. The method for manufacture of coated copper pillars according to claim 15 wherein the metal which is more noble than copper is selected from the group consisting of silver, palladium, platinum, rhodium, ruthenium, gold and alloys thereof with the proviso that silver and silver alloys are not selected as first metal layer if the second metal layer comprises silver or a silver alloy. 18. The method for manufacture of coated copper pillars according to claim 15 wherein the solder cap layer comprises tin. 19. The method for manufacture of coated copper pillars according to claim 15 wherein the second metal layer further comprises copper in the form of a copper-tin alloy. 20. The method for manufacture of coated copper pillars according to claim 15 wherein the second metal layer comprises tin and further comprises silver.

Assignees

Inventors

Classifications

  • relative to the surface, e.g. recessed, protruding · CPC title

  • changes in materials · CPC title

  • Intermetallic compounds · CPC title

  • in gaseous form, e.g. by CVD or PVD · CPC title

  • by plating, e.g. electroless plating or electroplating · CPC title

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What does patent US9331040B2 cover?
The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A…
Who is the assignee on this patent?
Atotech Deutschland Gmbh
What technology area does this patent fall under?
Primary CPC classification H10W72/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 03 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).