Semiconductor device

US9136263B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9136263-B2
Application numberUS-201414166937-A
CountryUS
Kind codeB2
Filing dateJan 29, 2014
Priority dateFeb 5, 2013
Publication dateSep 15, 2015
Grant dateSep 15, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a semiconductor device which uses a comb-like N-type MOS transistor as an ESD protection element and is capable of uniformly operating the entire comb-like N-type MOS transistor. By adjusting a length L of a gate electrode of the N-type MOS transistor used as the ESD protection element in accordance with the distance from a contact for fixing a substrate potential, which is provided on a guard ring around an outer periphery, respective portion of N-type MOS transistor represented as a comb teeth uniformly enter snap-back operation, permitting avoidance of local concentration of current and obtainment of a desired ESD tolerance.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device having an ESD protection element which utilizes an N-type MOS transistor having an integral structure of a plurality of transistors, the semiconductor device comprising: a plurality of drain regions and a plurality of source regions alternately arranged each other; a gate electrode formed between each of the plurality of drain regions and each of the plurality of source regions; and a substrate contact to which a metal interconnect…

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What does patent US9136263B2 cover?
Provided is a semiconductor device which uses a comb-like N-type MOS transistor as an ESD protection element and is capable of uniformly operating the entire comb-like N-type MOS transistor. By adjusting a length L of a gate electrode of the N-type MOS transistor used as the ESD protection element in accordance with the distance from a contact for fixing a substrate potential, which is provided…
Who is the assignee on this patent?
Seiko Instr Inc
What technology area does this patent fall under?
Primary CPC classification H10D89/815. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).