Device and method for alignment of vertically stacked wafers and die

Patent metadata

Field	Value
Publication number	US-9324660-B2
Application number	US-201314038574-A
Country	US
Kind code	B2
Filing date	Sep 26, 2013
Priority date	Dec 30, 2009
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

First claim

We claim:

1. A device, comprising:
a package, the package including:
a first die having a first surface and a second surface, the first die having a kerf region that surrounds an active region;
a plurality of first capacitive alignment structures arranged in a first pattern and formed on the first die closer to the first surface of the first die than to the second surface, the plurality of first capacitive alignment structures being in the active region of the first die;
a second die having a first surface and a second surface, the second surface of the second die positioned overlying the first surface of the first die, the second die having a kerf region that surrounds an active region; and
a plurality of second capacitive alignment structures arranged in the same first pattern as the first capacitive alignment structures and formed on the second die closer to the second surface than to the first surface, the plurality of second capacitive alignment structures being in the active region of the second die, the first and second capacitive alignment structures configured to form first and second plates, respectively, of a plurality of capacitors, the plurality of capacitors arranged in the first pattern.

2. The device of claim 1 , further comprising:
a third die having a first surface and a second surface;
a plurality of third capacitive alignment structures arranged in a second pattern and formed in the third die closer to the first surface of the third die than to the second surface;
the second die includes a plurality of fourth capacitive alignment structures arranged in the second pattern, the fourth capacitive alignment structures are formed in the second die closer to the first surface of the second die than to the second surface and are configured to form a plurality of capacitors with the plurality of third capacitive alignment structures in the third die.

3. The device of claim 2 wherein the first pattern of the second alignment structures is different from the second pattern of third alignment structures on the second die.

4. A method, comprising:
forming a first die having a first surface and a second surface;
forming the first die to have an active region and a kerf region;
forming a plurality of first capacitive alignment structures arranged in a first pattern on the first die in the active region;
forming the plurality of first capacitive alignment structures closer to the first surface of the first die than to the second surface;
forming a second die having a first surface and a second surface;
forming the first die to have an active region and a kerf region;
forming a plurality of second capacitive alignment structures arranged in the same first pattern as the first capacitive alignment structures on the second die in the active region of the second die; and
forming the plurality of second capacitive alignment structures closer to the second surface than to the first surface, the first and second capacitive alignment structures configured to form first and second plates, respectively, of a plurality of capacitors, the plurality of capacitors arranged in the first pattern.

5. The method of claim 4 , further comprising:
forming a third die having a first surface and a second surface;
forming a plurality of third capacitive alignment structures arranged in a second pattern in the third die closer to the first surface of the third die than to the second surface;
forming a plurality of fourth capacitive alignment structures arranged in the second pattern in the second die, the fourth capacitive alignment structures being closer to the first surface of the second die than to the second surface and are configured to form a plurality of capacitors with the plurality of third capacitive alignment structures in the third die.

6. The method of claim 5 , further comprising forming the first pattern of the second alignment structures to be different from the second pattern of third alignment structures on the second die.

7. A device, comprising:
a package, the package including:
a first die having a first surface and a second surface, the first die having an active area and a kerf area;
a plurality of first capacitive alignment structures arranged in a first pattern in the first die positioned near the first surface of the first die and spaced from the second surface of the first die, the plurality of first capacitive alignment structures being formed in the active region of the first die;
a second die having a first surface and a second surface, the second surface of the second die facing the first surface of the first die;
a plurality of second capacitive alignment structures arranged in the same first pattern as the first capacitive alignment structures and formed on the second die near the second surface of the second die and spaced from the first surface of the second die; and
a first plurality of capacitors, each having a first electrode and a second electrode, the first electrode being one of the first capacitive alignment structures and the second electrode being one of the second capacitive alignment structures, the plurality of capacitors arranged in the first pattern.

8. The device of claim 7 wherein the first electrode of each capacitor is a first conductive plate formed spaced from the first surface of the first die by a first distance, the first conductive plate being spaced from the second surface of the first die by a second distance that is greater than the first distance.

9. The device of claim 8 wherein the second electrode of each capacitor is a second conductive plate formed spaced from the second surface of the second die by a first distance, the second conductive plate being spaced from the first surface of the second die by a second distance that is greater than the first distance.

10. The device of claim 9 wherein the first and second conductive plates are substantially parallel to the first surface of the first die and the second surface of the second die, respectively.

11. The device of claim 7 , further comprising:
a third die having a first surface and a second surface;
a plurality of third capacitive alignment structures arranged in a second pattern in the third die positioned near the first surface of the third die and spaced from the second surface of the third die;
a plurality of fourth capacitive alignment structures arranged in the second patter in the second die positioned near the first surface of the second die and spaced from the second surface of the second die, the first surface of the second die facing the first surface of the third die.

12. A device, comprising:
a first capacitive alignment structure disposed on a first die of a first semiconductor wafer, the first die having an active area and a kerf region, the first capacitive alignment structures being in the active area;
a second capacitive alignment structure disposed on a second die of a second semiconductor wafer; and
circuitry on at least one of the semiconductor wafers that senses capacitance values and interfaces with capacitors formed from the first and second capacitive alignment structures to output an indication of alignment of the first and second capacitive alignment structures.

13. The device of claim 12 wherein the circuitry is provided on a same die as one or more of the first and second alignment structures.

Assignees

• St Microelectronics Inc

Inventors

• Zhang John H
• Kleemeier Walter
• Ferreira Paul
• Sampson Ronald K

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title