Semiconductor device
US-2024421048-A1 · Dec 19, 2024 · US
Integrated circuit packaging system with external interconnect and method of manufacture thereof
US9324641B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9324641-B2 |
| Application number | US-201213425286-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 20, 2012 |
| Priority date | Mar 20, 2012 |
| Publication date | Apr 26, 2016 |
| Grant date | Apr 26, 2016 |
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Abstract
Official abstract text for this publication.
A method of manufacture of an integrated circuit packaging system includes: providing a routable distribution layer on a leadframe; mounting an integrated circuit over the routable distribution layer; encapsulating with an encapsulation over the routable distribution layer; peeling the leadframe away from the routable distribution layer with a bottom distribution side of the routable distribution layer exposed from the encapsulation; and mounting an external interconnect on the routable distribution layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacture of an integrated circuit packaging system comprising: providing a routable distribution layer on a leadframe; mounting an integrated circuit over the routable distribution layer; encapsulating with an encapsulation over the integrated circuit and the routable distribution layer; peeling the leadframe away from the routable distribution layer with a bottom distribution side of the routable distribution layer exposed from the enca…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9324641B2 cover?
- A method of manufacture of an integrated circuit packaging system includes: providing a routable distribution layer on a leadframe; mounting an integrated circuit over the routable distribution layer; encapsulating with an encapsulation over the routable distribution layer; peeling the leadframe away from the routable distribution layer with a bottom distribution side of the routable distributi…
- Who is the assignee on this patent?
- Do Byung Tai, Arnel Senosa Trasporto, Chua Linda Pei Ee, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W70/421. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).