Semiconductor device

Patent metadata

Field	Value
Publication number	US-9312269-B2
Application number	US-201414272853-A
Country	US
Kind code	B2
Filing date	May 8, 2014
Priority date	May 16, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of memories, each of the plurality of memories comprising:
a volatile memory including a first data holding portion; and
a nonvolatile memory including a second data holding portion,
wherein:
the second data holding portion includes a first transistor and a first capacitor,
a first electrode of the first transistor is electrically connected to the first data holding portion,
a second electrode of the first transistor is electrically connected to a first electrode of the first capacitor,
the first electrode of the first capacitor and the first electrode of the first transistor are on a same layer, and
a second electrode of the first capacitor and a gate of the first transistor are on a same layer; and

a first wiring between the plurality of memories,
wherein:
the first wiring is configured to electrically connect gates of first transistors of the plurality of memories, and
a layer in which the first wiring is provided and a layer in which the gate of the first transistor is provided are different.

2. The semiconductor device according to claim 1 ,
wherein in the second data holding portion, the first transistor is turned off and charge is held between the second electrode of the first transistor and the first electrode of the first capacitor, whereby data stored in the first data holding portion is held.

3. The semiconductor device according to claim 1 , wherein the first transistor has a semiconductor layer comprising an oxide semiconductor.

4. The semiconductor device according to claim 1 , wherein the first transistor is a top-gate transistor.

5. The semiconductor device according to claim 1 , wherein the first data holding portion is a circuit including a second transistor having a semiconductor layer comprising silicon.

6. The semiconductor device according to claim 5 , wherein the first transistor is provided over the second transistor.

7. The semiconductor device according to claim 6 , each of the plurality of memories further comprising:
a second wiring between a layer in which the first transistor is provided and a layer in which the second transistor is provided,
wherein the second wiring is configured to electrically connect the first transistor and the second transistor.

8. A semiconductor device comprising:
a plurality of memories, each of the plurality of memories comprising:
a volatile memory including a first data holding portion and a second data holding portion; and
a nonvolatile memory including a third data holding portion and a fourth data holding portion,
wherein:
the third data holding portion includes a first transistor and a first capacitor,
the fourth data holding portion includes a second transistor and a second capacitor,
a first electrode of the first transistor is electrically connected to the first data holding portion,
a second electrode of the first transistor is electrically connected to a first electrode of the first capacitor,
a first electrode of the second transistor is electrically connected to the second data holding portion,
a second electrode of the second transistor is electrically connected to a first electrode of the second capacitor,
the first electrode of the first capacitor and the first electrode of the first transistor are on a same layer, and
a second electrode of the first capacitor, a second electrode of the second capacitor, a gate of the first transistor, and a gate of the second transistor are on a same layer; and

a first wiring between the plurality of memories,
wherein:
the first wiring is configured to electrically connect the gate of the first transistor and the gate of the second transistor, and
a layer in which the first wiring is provided and a layer in which the gate of the first transistor and the gate of the second transistor are provided are different.

9. The semiconductor device according to claim 8 ,
wherein in the third data holding portion, the first transistor is turned off and charge is held between the second electrode of the first transistor and the first electrode of the first capacitor, whereby data stored in the first data holding portion is held, and
wherein in the fourth data holding portion, the second transistor is turned off and charge is held between the second electrode of the second transistor and the first electrode of the second capacitor, whereby data stored in the second data holding portion is held.

10. The semiconductor device according to claim 8 , wherein each of the first transistor and the second transistor has a semiconductor layer comprising an oxide semiconductor.

11. The semiconductor device according to claim 8 , wherein each of the first transistor and the second transistor is a top-gate transistor.

12. The semiconductor device according to claim 8 ,
wherein the first data holding portion is a circuit including a third transistor, and the second data holding portion is a circuit including a fourth transistor, and
wherein each of the third transistor and the fourth transistor has a semiconductor layer comprising silicon.

13. The semiconductor device according to claim 12 , wherein the first transistor and the second transistor are provided over the third transistor.

14. The semiconductor device according to claim 13 , each of the plurality of memories further comprising:
a second wiring between a layer in which the first transistor and the second transistor are provided and a layer in which the third transistor and the fourth transistor are provided,
wherein the second wiring is configured to electrically connect the first transistor, the second transistor, the third transistor, and the fourth transistor.

Assignees

• Semiconductor Energy Lab

Inventors

• Kato Kiyoshi
• Onuki tatsuya

Classifications

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C14/0054 Primary

  in which the volatile element is a SRAM cell · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D30/6706 Primary

  for preventing leakage current  (TFTs characterised by the properties of the source or drain H10D30/6713) · CPC title