Semiconductor device and method of forming leadframe with conductive bodies for vertical electrical interconnect of semiconductor die

Patent metadata

Field	Value
Publication number	US-9312218-B2
Application number	US-201113106591-A
Country	US
Kind code	B2
Filing date	May 12, 2011
Priority date	May 12, 2011
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A semiconductor device has a semiconductor die mounted to a substrate. A leadframe has a base plate and integrated tie bars and conductive bodies. The tie bars include a down step with an angled surface and horizontal surface between the conductive bodies. The leadframe is mounted to the semiconductor die and substrate with the base plate disposed on a back surface of the semiconductor die and the conductive bodies disposed around the semiconductor die and electrically connected to the substrate. An encapsulant is deposited over the substrate and semiconductor die and into the down step of the tie bars. A conductive layer is formed over the conductive bodies to inhibit oxidation. The leadframe is singulated through the encapsulant in the down step and through the horizontal portion of the tie bars to electrically isolate the conductive bodies. A semiconductor package can be mounted to the substrate and semiconductor die.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a first substrate;
disposing a first semiconductor die over the first substrate;
providing a leadframe including a base plate and a plurality of tie bars and conductive bodies, the tie bars including a down step with a slanted surface and a horizontal surface between the conductive bodies;
disposing the leadframe over the first semiconductor die and first substrate with the base plate disposed over a non-active surface of the first semiconductor die and the conductive bodies disposed adjacent to the first semiconductor die and electrically connected to the first substrate;
depositing an encapsulant over the first substrate and around the first semiconductor die and into the down step of the tie bars; and
forming a recess in the encapsulant and extending through the tie bars to electrically isolate the conductive bodies from the base plate.

2. The method of claim 1 , further including forming the recess through the horizontal surface of the tie bars to electrically isolate the conductive bodies from the base plate.

3. The method of claim 1 , further including:
providing a second substrate;
disposing a second semiconductor die over the second substrate; and
disposing the second substrate and second semiconductor die over the first substrate and first semiconductor die.

4. The method of claim 3 , further including:
forming an interconnect structure over the second substrate; and
bonding the interconnect structure to the conductive bodies.

5. The method of claim 1 , further including forming a conductive layer over the conductive bodies.

6. The method of claim 1 , wherein the conductive bodies are offset within the tie bars.

7. A method of making a semiconductor device, comprising:
providing a first substrate;
disposing a first semiconductor die over the first substrate;
providing a leadframe including a plurality of tie bars and conductive bodies, the tie bars including a down step between the conductive bodies;
disposing the leadframe over the first semiconductor die and first substrate with the conductive bodies disposed adjacent to the first semiconductor die and electrically connected to the first substrate;
depositing an encapsulant over the first substrate and around the first semiconductor die and into the down step of the tie bars;
forming a recess partially through the encapsulant and through the tie bars to electrically isolate the conductive bodies; and
singulating through the leadframe with the recess remaining after singulation.

8. The method of claim 7 , wherein the down step of the tie bars includes an angled surface and horizontal surface.

9. The method of claim 7 , wherein the leadframe includes a base plate.

10. The method of claim 7 , further including:
providing a second substrate;
disposing a second semiconductor die over the second substrate; and
disposing the second substrate and second semiconductor die over the first substrate and first semiconductor die.

11. The method of claim 10 , further including:
forming an interconnect structure over the second substrate; and
bonding the interconnect structure to the conductive bodies.

12. The method of claim 7 , further including forming a conductive layer over the conductive bodies.

13. The method of claim 7 , wherein the conductive bodies are offset within the tie bars.

14. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
providing a leadframe including a plurality of tie bars and conductive bodies;
disposing the leadframe over the first semiconductor die with the conductive bodies disposed adjacent to the first semiconductor die;
depositing an encapsulant over the first semiconductor die;
forming a recess in the encapsulant and extending through the tie bars; and
singulating through the encapsulant with the recess remaining after singulation.

15. The method of claim 14 , wherein the tie bars include a down step between the conductive bodies and the down step of the tie bars includes an angled surface and horizontal surface.

16. The method of claim 14 , wherein the leadframe includes a base plate.

17. The method of claim 14 , further including:
providing a first substrate;
disposing the first semiconductor die over the first substrate; and
disposing the leadframe over the first semiconductor die and first substrate.

18. The method of claim 17 , further including:
providing a second substrate;
disposing a second semiconductor die over the second substrate; and
disposing the second substrate and second semiconductor die over the first substrate and first semiconductor die.

19. The method of claim 14 , further including forming a conductive layer over the conductive bodies.

20. The method of claim 14 , further including planarizing the encapsulant to expose the conductive bodies from the encapsulant.

Assignees

• Choi Daesik
• Park Soosan
• Shin Hangil
• Stats Chippac Ltd

Inventors

• Choi Daesik
• Park Soosan
• Shin Hangil

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title