Method for processing an oxygen containing semiconductor body

US9312120B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9312120-B2
Application numberUS-201414473890-A
CountryUS
Kind codeB2
Filing dateAug 29, 2014
Priority dateAug 29, 2014
Publication dateApr 12, 2016
Grant dateApr 12, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A method for processing a semiconductor body is disclosed. In an embodiment, the method includes reducing an oxygen concentration in a silicon wafer in a first region adjoining a first surface of the silicon wafer by a first heat treatment, creating vacancies in a crystal lattice of the wafer at least in a second region adjoining the first region by implanting particles via the first surface into the wafer and forming oxygen precipitates in the second region by a second heat treatment.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: reducing an oxygen concentration in a silicon wafer in a first region adjoining a first surface of the silicon wafer by a first heat treatment; creating vacancies in a crystal lattice of the wafer at least in a second region adjoining the first region by implanting particles via the first surface into the wafer; and forming oxygen precipitates in the second region by a second heat treatment. 2. The method of claim 1 , wherein a temperature in the first heat treatment is higher than 1000° C. 3. The method of claim 1 , wherein a duration of the first treatment is longer than 1 hour. 4. The method of claim 1 , wherein a duration of the first treatment is longer than 4 hours. 5. The method of claim 1 , further comprising: measuring the oxygen concentration in the first region before the first heat treatment; and adjusting at least one of a temperature in the first heat treatment, and a duration of the first heat treatment based on the measuring. 6. The method of claim 1 , wherein the first heat treatment is configured to reduce the oxygen concentration in the first region to below 6E17 cm −3 . 7. The method of claim 1 , wherein the first heat treatment is configured to reduce the oxygen concentration in the first region to below 5E17 cm −3 . 8. The method of claim 1 , wherein the first heat treatment is adapted to form the first region with a depth of between 2-15 μm as seen from the first surface. 9. The method of claim 1 , wherein the particles include at least one of protons and helium atoms. 10. The method of claim 1 , wherein implanting the particles comprises implanting the particles at a dose of between 5E13 cm −2 and 1E15 cm −2 . 11. The method of claim 1 , wherein creating vacancies comprises generating vacancies in a concentration of between 1E17 cm −3 and 1E19 cm −3 . 12. The method of claim 1 , wherein a temperature in the second heat treatment is selected from a range of between 700° C. and 1050° C. 13. The method of claim 12 , wherein a duration of the second heat treatment is between 1 hour and 30 hours. 14. The method of claim 13 , wherein the second heat treatment comprises: heating at least the second region to a temperature of between 750° C. and 850° C. for between 1 hour and 10 hours, and heating at least the second region to a temperature of between 950° C. and 1100° C. for between 10 hours and 20 hours. 15. The method of claim 1 , further comprising: creating vacancies in the crystal lattice of the wafer in a third region adjoining a second surface opposite the first surface before the second heat treatment. 16. The method of claim 15 , wherein creating vacancies in the third region comprises at least one of implanting particles into the second surface, and subjecting the second surface to a heat treatment in a nitrogen containing atmosphere. 17. The method of claim 16 , further comprising: forming a protection layer on the first surface before the heat treatment in the nitrogen containing atmosphere. 18. The method of claim 17 , wherein the protection layer is an oxide layer. 19. The method of claim 1 , further comprising: forming an epitaxial layer on the first surface. 20. The method of claim 1 , further comprising: before forming the oxygen precipitates, forming nucleation seeds in the second region. 21. The method of claim 1 , further comprising: before the first heat treatment, driving interstitial silicon atoms from the first surface into the silicon wafer. 22. The method of claim 21 , wherein driving the interstitial atoms into the silicon wafer comprises forming an oxide on the first surface. 23. A semiconductor wafer comprising: a first surface; a first region, a second region, and a third region, wherein the first region adjoins the first surface, and wherein the second region is between the first region and the third region, wherein a minimum concentration of oxygen precipitates in the third region is higher than a maximum concentration of oxygen precipitates in the first region, and wherein a minimum concentration of oxygen precipitates in the second region is higher than a maximum concentration of oxygen precipitates in the third region. 24. The semiconductor wafer of claim 23 , wherein the minimum concentration of oxygen precipitates in the third region is at least 10 times the maximum concentration of oxygen precipitates in the first region. 25. The semiconductor wafer of claim 23 , wherein the minimum concentration of oxygen precipitates in the second region is at least 3 times the maximum concentration of oxygen precipitates in the third region.

Assignees

Inventors

Classifications

  • Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • H10P95/90Primary

    Thermal treatments, e.g. annealing or sintering · CPC title

  • by making porous regions on the surface · CPC title

  • comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement · CPC title

  • characterised by multiple measurements, corrections, marking or sorting processes · CPC title

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What does patent US9312120B2 cover?
A method for processing a semiconductor body is disclosed. In an embodiment, the method includes reducing an oxygen concentration in a silicon wafer in a first region adjoining a first surface of the silicon wafer by a first heat treatment, creating vacancies in a crystal lattice of the wafer at least in a second region adjoining the first region by implanting particles via the first surface in…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10P95/90. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 12 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).