High productivity combinatorial workflow to screen and design chalcogenide materials as non volatile memory current selector

Patent metadata

Field	Value
Publication number	US-9305791-B2
Application number	US-201314135505-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	Mar 13, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Combinatorial workflow is provided for evaluating materials and processes for current selector devices in a cross point memory array. Blanket layers, metal-insulator-metal devices, and compete memory structures are combinatorially fabricated on multiple regions of a substrate, with each region having a different material and process condition for the current selector devices. The current selector devices are then characterized, and the data are compared to obtain the optimum materials and processes.

First claim

What is claimed is:

1. A method for development of cross point memory arrays, the method comprising:
forming a first layer over a substrate,
wherein the first layer comprises a chalcogenide material positioned in different site isolated regions of the substrate,
wherein a process condition used for forming the first layer is varied in a combinatorial manner between the different site isolated regions,
wherein the first layer is operable as an ovonic threshold switch; and

forming a first electrode over the first layer.

2. A method as in claim 1 further comprising
forming a second electrode over the substrate;
forming a second layer over the second electrode,
wherein the second layer comprises a chalcogenide material,
wherein the second layer is operable as a phase change material;

forming a third electrode over the second layer.

3. A method as in claim 1 further comprising
forming a second electrode over the substrate;
forming a second layer over the second electrode,
wherein the second layer comprises a metal oxide material,
wherein the second layer is operable as a switching layer;

forming a third electrode over the second layer.

4. A method as in claim 1 wherein a material composition of the first layer is varied in a combinatorial manner.

5. A method as in claim 1 wherein the combinatorial processing comprises at least one of physical vapor deposition, co-evaporation, atomic layer deposition, or thermal processing.

6. A method for the development of cross point memory arrays, the method comprising:
defining site isolated regions on a substrate;
forming a first layer in each of the site isolated regions,
wherein the first layer comprises a chalcogenide material,
wherein the first layer is operable as an ovonic threshold switch,
wherein a process condition of the first layer formation is varied in a combinatorial manner between the site isolated regions; and

measuring a structural characteristic of the first layer within each site isolated region.

7. A method as in claim 6 further comprising forming a memory device in each site isolated region, wherein each memory device is operable as a phase change memory device or a resistive switching memory device.

8. A method as in claim 6 wherein a composition is varied in a combinatorial manner between the site isolated regions comprising varying a number of elements in the composition.

9. A method as in claim 6 wherein a composition is varied in a combinatorial manner between the site isolated regions comprising varying a ratio of the elements in the first layer.

10. A method as in claim 6 wherein varying the process condition in the combinatorial manner between the site isolated regions comprises varying a temperature of a heat treatment of the first layer.

11. A method as in claim 6 wherein varying the process condition in the combinatorial manner between the site isolated regions comprises varying an integration process of the first layer with the memory device.

12. A method as in claim 6 wherein measuring a structural characteristic comprises measuring a phase stability of the first layer material.

13. A method as in claim 6 wherein measuring an electrical characteristic comprises measuring at least an endurance, a variability, a reliability, or a performance of the memory device.

14. A method for the development of cross point memory arrays, the method comprising:
defining a plurality of site isolated regions on a substrate;
forming a first electrode in each site isolated region;
forming a first layer over the first electrode in each of the site isolated regions,
wherein the first layer comprises a chalcogenide material,
wherein the first layer is operable as an ovonic threshold switch,
wherein a process condition of the first layer formation is varied in a combinatorial manner between the site isolated regions;

forming a second electrode over the first layer,
measuring an electrical characteristic of the first layer within each site isolated region.

15. A method as in claim 14 further comprising forming a memory device in each site isolated region, wherein the memory device is operable as a phase change memory device or a resistive switching memory device.

16. A method as in claim 14 wherein a composition is varied in a combinatorial manner between the site isolated regions comprising varying a number of elements in the first layer.

17. A method as in claim 14 wherein a composition is varied in a combinatorial manner between the site isolated regions comprising varying a ratio of elements in the first layer.

18. A method as in claim 14 wherein varying the process condition in the combinatorial manner between the site isolated regions comprises varying a temperature of a heat treatment of the first layer.

Assignees

• Intermolecular Inc

Inventors

• Hashim Imran

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/20

  characterised by the properties tested or measured, e.g. structural or electrical properties · CPC title

• H10P72/0462

  characterised by the construction of the processing chambers, e.g. modular processing chambers · CPC title

• H10P72/0416

  with the semiconductor substrates being dipped in baths or vessels · CPC title