Receiver circuit for correcting skew, semiconductor apparatus and system including the same

Patent metadata

Field	Value
Publication number	US-9304532-B2
Application number	US-201414244010-A
Country	US
Kind code	B2
Filing date	Apr 3, 2014
Priority date	Dec 30, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A receiver circuit includes a deserialization unit, a sampling clock control unit and a sampling clock generation unit. The deserialization unit is configured to receive sampling clock signals, sample a plurality of input data signals, and generate a plurality of internal data signals. The sampling clock control unit is configured to generate a delay control signal and a synchronization completion signal in response to the plurality of internal data signals and a first group of clock signals. The sampling clock generation unit delays the first group of clock signals and provides the delayed first group of clock signals as the sampling clock signals in response to the delay control signal, and provides a second group of clock signals having a phase leading by a predetermined amount with respect to the first group of clock signals, as the sampling clock signals in response to the synchronization completion signal.

First claim

What is claimed is:

1. A receiver circuit comprising:
a deserialization unit configured to receive sampling clock signals, sample a plurality of input data signals, and generate a plurality of internal data signals;
a sampling clock control unit configured to generate a delay control signal and a synchronization completion signal in response to the plurality of internal data signals and a first group of clock signals; and
a sampling clock generation unit configured to delay the first group of clock signals and provide the delayed first group of clock signals as the sampling clock signals in response to the delay control signal, and configured to provide a second group of clock signals having a phase leading by a predetermined amount with respect to the phase of the first group of clock signals as the sampling clock signals in response to the synchronization completion signal.

2. The receiver circuit of claim 1 , wherein the sampling clock control unit comprises:
a synchronization detection unit configured to generate the synchronization completion signal by detecting levels of the plurality of internal data signals; and
a delay control unit configured to generate the delay control signal in response to the first group of clock signals until the synchronization completion signal is enabled.

3. The receiver circuit of claim 2 , wherein when one of the plurality of input data signals has a high level, the synchronization detection unit enables the synchronization completion signal when the plurality of internal data signals have a low level.

4. The receiver circuit of claim 1 , wherein the sampling clock generation unit comprises a delay selection unit configured to delay the first group of clock signals by an amount of a unit time period in response to the delay control signal, and provide one of the delayed first group of clock signals and the second group of clock signals as the sampling clock signals in response to the synchronization completion signal.

5. The receiver circuit of claim 4 , wherein the sampling clock generation unit further comprises a phase interpolation unit configured to generate the second group of clock signals based on the first group of clock signals.

6. The receiver circuit of claim 4 , wherein the delay selection unit comprises:
a delay unit configured to generate a delayed first group of clock signals, that are sequentially delayed by an amount of a unit time period in response to the delay control signal; and
a multiplexer configured to provide one of the output of the delay unit and the second group of clock signals as the sampling clock signals in response to the synchronization completion signal.

7. The receiver circuit of claim 1 , wherein the predetermined amount of phase corresponds to one half of a window of the plurality of input data signals.

8. A method for correcting a skew in a semiconductor apparatus comprising:
at a deserialization unit, receiving a first group of clock signals, sampling a plurality of input data signals, and generating a plurality of internal data signals;
delaying the first group of clock signals and synchronizing edges of the plurality of input data signals with edges of the first group of clock signals in response to the plurality of internal data signals;
providing a second group of clock signals having a phase leading by a predetermined amount with respect to the first group of clock signals, to the deserialization unit in response to the synchronization of the edges; and
at the deserialization unit, receiving the second group of clock signals, sampling the plurality of input data signals, and generating the plurality of internal data signals.

9. The method for correcting a skew in a semiconductor apparatus in claim 8 , wherein a clock signal is used to sample the a data signal according to an input order of the plurality of input data signals.

10. The method for correcting a skew in a semiconductor apparatus in claim 8 , wherein one of the plurality of input data signals has a high level, and
wherein the synchronizing the edges of the plurality of input data signals with the edges of the first group of clock signals delays the first group of clock signals until a synchronization completion signal is enabled, and generates the synchronization completion signal when the plurality of internal data signals sampled using the delayed first group of clock signals have a low level.

11. The method for correcting a skew in a semiconductor apparatus in claim 10 , wherein the providing the second group of clock signals is performed in response to the synchronization completion signal.

12. The method for correcting a skew in a semiconductor apparatus in claim 8 , wherein the predetermined amount of phase corresponds to one half of a window of the plurality of input data signals.

13. The method for correcting a skew in a semiconductor apparatus in claim 8 , further comprising generating the second group of clock signals based on the first group of clock signals.

14. The method for correcting a skew in a semiconductor apparatus in claim 8 , further comprising, at a master device, providing the plurality of input data signals having a predetermined pattern to the semiconductor apparatus during a training operation.

Assignees

• Sk Hynix Inc

Inventors

• Jung Inhwa

Classifications

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title