Elimination of undesirable current paths in GSHE-MTJ based circuits

Patent metadata

Field	Value
Publication number	US-9300295-B1
Application number	US-201514626920-A
Country	US
Kind code	B1
Filing date	Feb 19, 2015
Priority date	Oct 30, 2014
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

Systems and methods pertain to avoiding undesirable current paths or sneak paths in spintronic logic gates formed from Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) elements. Sneak path prevention logic is coupled to the GSHE MTJ elements, to prevent the sneak paths. The sneak path prevention logic may include one or more transistors coupled to the one or more GSHE MTJ elements, to restrict write current from flowing from an intended pipeline stage to an unintended pipeline stage during a write operation. The sneak path prevention logic may also include one or more diodes coupled to the one or more GSHE MTJ elements to prevent a preset current from flowing into input circuitry or a charge current generation circuit. A preset line may be coupled to the one or more GSHE MTJ elements to divert preset current from flowing into unintended paths.

First claim

What is claimed is:

1. A spintronic logic circuit comprising:
one or more Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) elements; and
sneak path prevention logic coupled to the GSHE MTJ elements, the sneak path prevention logic configured to prevent sneak paths comprising the flow of charge current in unintended paths in the spintronic logic circuit.

2. The spintronic logic circuit of claim 1 comprising:
two or more pipeline stages comprising the one or more GSHE MTJ elements; and
a charge current generation circuit configured to provide write current to the one or more GSHE MTJ elements,
wherein the sneak path prevention logic comprises one or more transistors coupled to the one or more GSHE MTJ elements, the transistors configured to restrict the write current from flowing from an intended pipeline stage to an unintended pipeline stage during a write operation.

3. The spintronic logic circuit of claim 1 , wherein the sneak path prevention logic comprises one or more diodes coupled to the one or more GSHE MTJ elements and configured to prevent a preset current from flowing into input circuitry or a charge current generation circuit.

4. The spintronic logic circuit of claim 3 , further comprising a preset line configured to provide an alternative path for the preset current.

5. The spintronic logic circuit of claim 1 comprising a stream bit adder, the stream bit adder comprising a single bit adder configured to add a stream of one or more bits in one or more pipeline stages.

6. The spintronic logic circuit of claim 5 , wherein the single bit adder comprises:
logic configured to add a first input bit, a second input bit, and a carry-in bit to generate a carry-out bit and a sum bit, wherein the carry-out bit is coupled to the carry-in bit.

7. A method of preventing sneak paths in a spintronic logic circuit, the method comprising:
coupling one or more sneak path prevention logic elements to one or more Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) elements of the spintronic logic circuit; and
preventing sneak paths comprising the flow of charge current in unintended paths in the spintronic logic circuit using the sneak path prevention logic elements.

8. The method of claim 7 comprising:
partitioning the one or more GSHE MTJ elements into two or more pipeline stages; and
providing write current to the GSHE MTJ elements from a charge current generation circuit, wherein preventing the sneak paths comprises preventing the write current from flowing from an intended pipeline stage to an unintended pipeline stage during a write operation.

9. The method of claim 8 , wherein the sneak path prevention logic comprises one or more transistors coupled to the one or more GSHE MTJ elements.

10. The method of claim 8 , wherein the sneak path prevention logic comprises one or more diodes coupled to the one or more GSHE MTJ elements.

11. The method of claim 7 , comprising preventing a preset current from flowing into input circuitry or a charge current generation circuit wherein the sneak path prevention logic comprises one or more diodes coupled to the one or more GSHE MTJ elements.

12. The method of claim 11 , further comprising coupling a preset line to one or more GSHE MTJ elements to provide an alternative path for the preset current.

13. The method of claim 7 comprising configuring the spintronic logic circuit as a stream bit adder, the stream bit adder comprising a single bit adder for adding a stream of one or more bits in one or more pipeline stages.

14. The method of claim 13 , comprising adding a first input bit, a second input bit, and a carry-in bit in the single bit adder in a first pipeline stage to generate a carry-out bit and a sum bit, and coupling the carry-out bit to the carry-in bit.

15. A spintronic logic circuit comprising:
one or more Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) elements; and
means for preventing sneak paths comprising the flow of charge current in unintended paths in the spintronic logic circuit.

16. The spintronic logic circuit of claim 15 comprising:
two or more pipeline stages comprising the one or more GSHE MTJ elements; and
wherein the means for preventing sneak paths comprises means for preventing write current from flowing from an intended pipeline stage to an unintended pipeline stage during a write operation.

17. The spintronic logic circuit of claim 16 , wherein the means for preventing sneak paths comprises one or more transistors coupled to the one or more GSHE MTJ elements.

18. The spintronic logic circuit of claim 16 , wherein the means for preventing sneak paths comprises one or more diodes coupled to the one or more GSHE MTJ elements.

19. The spintronic logic circuit of claim 15 , wherein the means for preventing sneak paths comprises means for preventing a preset current from flowing into input circuitry or a charge current generation circuit.

20. The spintronic logic circuit of claim 19 , further comprising means for providing an alternative path for the preset current.

Assignees

• Qualcomm Inc

Inventors

• Zhang Yaojun
• Wu Wenqing
• Yuen Kendrick Hoy Leong
• Arabi Karim

Classifications

• G11C11/18

  using Hall-effect devices · CPC title

• H03K19/18

  using galvano-magnetic devices, e.g. Hall-effect devices · CPC title

• H03K3/45

  by the use, as active elements, of non-linear magnetic or dielectric devices · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• H03K19/00346 Primary

  Modifications for eliminating interference or parasitic voltages or currents · CPC title