Digital technique for excess loop delay compensation in a continuous-time delta sigma modulator

Patent metadata

Field	Value
Publication number	US-9294120-B2
Application number	US-201514822061-A
Country	US
Kind code	B2
Filing date	Aug 10, 2015
Priority date	Aug 20, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A continuous time delta sigma modulator includes a quantizer, a buffer module, and a reference module. The quantizer includes a comparator that updates a digital output each cycle of a clock signal based on a comparison of a reference potential with an input generated based on a sample of an analog signal. The buffer module receives the digital output, stores the digital output for a predetermined delay period, and outputs the digital output after the predetermined delay period as a delayed digital output. The predetermined delay period is less than one cycle of the clock signal. The reference module selectively varies the reference potential based on the delayed digital output.

First claim

What is claimed is:

1. A continuous time delta sigma modulator, comprising:
a quantizer including a comparator that updates a digital output each cycle of a clock signal based on a comparison of a reference potential with an input generated based on a sample of an analog signal;
a buffer module that receives the digital output, that stores the digital output for a predetermined delay period, and that outputs the digital output after the predetermined delay period as a delayed digital output,
wherein the predetermined delay period is less than one cycle of the clock signal; and
a reference module that selectively varies the reference potential based on the delayed digital output.

2. The continuous time delta sigma modulator of claim 1 wherein the predetermined delay period is one-half of one cycle of the clock signal.

3. The continuous time delta sigma modulator of claim 1 wherein the reference module includes:
a switching module that includes a plurality of switching devices and a plurality of resistors that regulate the reference potential; and
a switch control module that controls states of the switching devices based on the delayed digital output.

4. The continuous time delta sigma modulator of claim 1 further comprising:
a digital to analog converter (DAC) that converts the delayed digital output into an analog value; and
an integrator that generates the input based on the sample of the analog signal and the analog value.

5. The continuous time delta sigma modulator of claim 4 further comprising:
a subtractor that subtracts the analog value from the sample of the analog signal to produce an output,
wherein the integrator generates the input based on a mathematical integral of the output of the subtractor.

6. The continuous time delta sigma modulator of claim 1 wherein:
the quantizer further includes N additional comparators that update N additional digital outputs each cycle of a clock signal based on comparisons of N additional reference potentials, respectively, with the input generated based on the sample of the analog signal;
N is an integer greater than zero;
the buffer module further stores the N digital additional outputs for the predetermined delay period and outputs the N digital output after the predetermined delay period as N additional delayed digital outputs, respectively; and
the reference module selectively varies the N additional reference potentials based on the N additional delayed digital outputs.

7. The continuous time delta sigma modulator of claim 1 wherein a frequency of the clock signal is greater than a sampling frequency of the analog signal.

8. A continuous time delta sigma modulator, comprising:
a quantizer that includes N comparators that generate N digital outputs based on comparisons of (i) an input generated based on a sample of an analog signal with (ii) N reference potentials, respectively;
a switching module that includes a plurality of switching devices and a plurality of resistors and that, based on states of the switching devices, outputs the N reference potentials; and
a switch control module that controls the states of the switching devices based on the N digital outputs.

9. The continuous time delta sigma modulator of claim 8 further comprising a buffer module that receives the N digital outputs, that delays outputting the N digital outputs for less than one cycle of a clock signal, and that outputs the N delayed digital outputs to the switch control module,
wherein the switch control module controls the states of the switching devices based on the N delayed digital outputs.

10. The continuous time delta sigma modulator of claim 9 wherein the buffer module delays outputting the N digital outputs for one-half of the cycle of the clock signal.

11. The continuous time delta sigma modulator of claim 9 wherein the N comparators update the N digital outputs once per cycle of the clock signal.

12. The continuous time delta sigma modulator of claim 9 further comprising:
a digital to analog converter (DAC) that converts the N delayed digital outputs into an analog value; and
an integrator that generates the input based on the sample of the analog signal and the analog value.

13. The continuous time delta sigma modulator of claim 12 further comprising:
a subtractor that subtracts the analog value from the sample of the analog signal to produce an output,
wherein the integrator generates the input based on a mathematical integral of the output of the subtractor.

14. A method comprising:
using a comparator of a quantizer of a continuous time delta sigma modulator, updating a digital output each cycle of a clock signal based on a comparison of a reference potential with an input generated based on a sample of an analog signal;
receiving, using a buffer module, the digital output from the comparator;
storing, using the buffer module, the digital output for a predetermined delay period outputting the digital output after the predetermined delay period as a delayed digital output,
wherein the predetermined delay period is less than one cycle of the clock signal; and
selectively varying the reference potential based on the delayed digital output.

15. The method of claim 14 wherein the predetermined delay period is one-half of one cycle of the clock signal.

16. The method of claim 14 wherein selectively varying the reference potential includes:
controlling states of a plurality of switching devices based on the delayed digital output.

17. The method of claim 14 further comprising:
converting the delayed digital output into an analog value using a digital to analog converter (DAC); and
generating the input based on the sample of the analog signal and the analog value.

18. The method of claim 17 further comprising:
subtracting, using a subtractor, the analog value from the sample of the analog signal to produce an output, wherein generating the input includes generating the input the input based on a mathematical integral of the output of the subtractor.

19. The method of claim 14 further comprising:
updating, using N additional comparators of the quantizer of the continuous time delta sigma modulator, based on comparisons of N additional reference potentials, respectively, with the input generated based on the sample of the analog signal,
wherein N is an integer greater than zero;
storing, using the buffer module, the N digital additional outputs for the predetermined delay period and outputting the N digital output after the predetermined delay period as N additional delayed digital outputs, respectively; and
selectively varying the N additional reference potentials based on the N additional delayed digital outputs.

20. The method of claim 14 wherein a frequency of the clock signal is greater than a sampling frequency of the analog signal.

Assignees

• Maxim Integrated Products

Inventors

• Zhang Yi
• Elliott Phillip
• Liu Ed
• Qian Yang
• Ostrem Geir
• Scampini John Frank

Classifications

• H03M3/422 Primary

  having one quantiser only · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M3/37 Primary

  Compensation or reduction of delay or phase error · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title