FinFET devices

Patent metadata

Field	Value
Publication number	US-9293584-B2
Application number	US-201113287331-A
Country	US
Kind code	B2
Filing date	Nov 2, 2011
Priority date	Nov 2, 2011
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Disclosed are various embodiments of FinFET semiconductor devices. A pair of matched capacitors can be formed that share a common source, drain and/or channel. Accordingly, the capacitance characteristics of each capacitor can be manufactured such that they are similar to one another. A resistor manufactured by employing FinFET techniques is also described. The resistor can be manufactured with an effective length that is greater than a distance traversed along a substrate by the resistor.

First claim

Therefore, having thus described the invention, at least the following is claimed:

1. A method, comprising:
forming a fin structure in a semiconductor substrate, the fin structure having a first side surface and a second side surface, the first side surface and the second side surface opposing each other relative to the fin structure;
forming a first trench adjacent to the first side surface and a second trench adjacent to the second side surface in the semiconductor substrate;
forming an isolation layer within the first trench and the second trench;
forming an insulator layer adjacent to the first side surface and the second side surface;
forming a conductor layer adjacent to the insulator layer;
etching the conductor layer to form two separate and distinct conductor structures, wherein:
one of the two separate and distinct conductor structures is adjacent to the isolation layer within the first trench, and another of the two separate and distinct conductor structures is adjacent to the isolation layer within the second trench; and
the two separate and distinct conductor structures share the fin structure;

forming a first bridge structure that is connected to the one of the two separate and distinct conductor structures and that extends orthogonally with respect to the one of the two separate and distinct conductor structures; and
forming a second bridge structure that is connected to the another of the two separate and distinct conductor structures and that extends orthogonally with respect to the another of the two separate and distinct conductor structures, wherein the first bridge structure is distinct and separate from the second bridge structure.

2. The method of claim 1 , further comprising:
forming a second fin structure in the semiconductor substrate, the second fin structure having a third side surface and a fourth side surface, the third side surface and the fourth side surface opposing each other relative to the second fin structure, the second fin structure further being adjacent to the first trench; and
forming another insulator layer adjacent to the third side surface.

3. The method of claim 2 , further comprising:
forming the conductor layer adjacent to the second fin structure.

4. The method of claim 1 , further comprising:
depositing a hard mask layer in the semiconductor substrate;
depositing a photoresist on the hard mask layer in a position corresponding to a location of the fin structure, the photoresist sized to have a surface area of a cross-sectional area of the fin structure; and
etching the hard mask layer to form the fin structure.

5. The method of claim 4 , further comprising:
depositing an insulator material subsequent to etching the hard mask layer to form the fin structure, the insulator material being in contact with the fin structure.

6. The method of claim 1 , wherein the conductor layer comprises one of: a metal or a doped polysilicon.

7. The method of claim 1 , wherein the semiconductor substrate comprises silicon.

8. The method of claim 1 , wherein the insulator layer comprises one of: a high-k dielectric material or an oxide insulator material.

9. The method of claim 1 , further comprising:
forming an n-well in the semiconductor substrate.

10. The method of claim 9 , wherein the n-well is positioned within the semiconductor substrate beneath the fin structure.

11. The method of claim 1 , wherein the first bridge structure and the second bridge structure have interlocking comb-shaped arrays of conductor structures with respect to each other.

12. A semiconductor device, comprising:
a fin structure in a semiconductor substrate, the fin structure having a first side surface and a second side surface, the first side surface and the second side surface opposing each other relative to the fin structure;
a first trench adjacent to the first side surface and a second trench adjacent to the second side surface in the semiconductor substrate;
a first isolation structure within the first trench and a second isolation structure within the second trench;
a first insulator structure adjacent to the first side surface and a second insulator structure adjacent to the second side surface;
a first conductor structure adjacent to the first isolation structure that is within the first trench and a second conductor structure adjacent to the second isolation structure that is within the second trench, wherein the first conductor structure and the second conductor structure share the fin structure;
a first bridge structure that is connected to the first conductor structure and that extends orthogonally with respect to the first conductor structure; and
a second bridge structure that is connected to the second conductor structure and that extends orthogonally with respect to the second conductor structure, wherein the first bridge structure is distinct and separate from the second bridge structure.

13. The semiconductor device of claim 12 , wherein
the first conductor structure comprises at least one of: a metal or a doped polysilicon;
the second conductor structure comprises at least one of: the metal or the doped polysilicon;
the first insulator structure comprises at least one of: a high-k dielectric material or an oxide insulator material; and
the second insulator structure comprises at least one of: the high-k dielectric material or the oxide insulator material.

14. The semiconductor device of claim 12 , wherein
the first conductor structure is directly adjacent to the first insulator structure.

15. The semiconductor device of claim 14 , wherein
the second conductor structure is directly adjacent to the second insulator structure.

16. The semiconductor device of claim 12 , wherein
the first conductor structure is in contact with the first insulator structure.

17. The semiconductor device of claim 16 , wherein
the second conductor structure is in contact with the second insulator structure.

18. The semiconductor device of claim 12 , wherein the first conductor structure has a same size as the second conductor structure.

19. The semiconductor device of claim 12 , wherein the first isolation structure is in contact with the first side surface of the fin structure and the semiconductor substrate.

20. The semiconductor device of claim 12 , wherein the first bridge structure and the second bridge structure have interlocking comb-shaped arrays of conductor structures with respect to each other.

Assignees

• Chen Xiangdong
• Chen Henry
• Woo Agnes
• Xia Wei
• Broadcom Corp

Inventors

• Chen Xiangdong
• Chen Henry
• Woo Agnes
• Xia Wei

Classifications

• H10D30/6217

  having non-uniform gate electrodes, e.g. gate conductors having varying doping · CPC title

• H10D30/6215

  having multiple independently-addressable gate electrodes · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D1/66

  Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title