Through-substrate vias with improved connections

Patent metadata

Field	Value
Publication number	US-9293366-B2
Application number	US-76925110-A
Country	US
Kind code	B2
Filing date	Apr 28, 2010
Priority date	Apr 28, 2010
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

First claim

What is claimed is:

1. A device comprising:
a substrate;
a plurality of dielectric layers over the substrate;
a plurality of metallization layers formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers lower than the top level of the plurality of metallization layers comprises a metal pad;
an interlayer dielectric (ILD) disposed over the substrate and under the plurality of metallization layers, the bottommost surface of the metal pad above the topmost surface of the ILD;
a through-substrate via (TSV) extending from the top level of the plurality of the dielectric layers to a bottom surface of the substrate;
a deep conductive via extending from the top level of the plurality of dielectric layers and landing on the metal pad, wherein the deep conductive via is a structure different from the metal pad;
a metal line over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via;
a passivation layer over the metal line; and
a metal bump over the passivation layer, the metal bump disposed outside a lateral extent of the metal line.

2. The device of claim 1 , wherein the metal pad is positioned in the bottom level of the plurality of metallization layers.

3. The device of claim 1 , wherein a first horizontal dimension of the TSV is greater than a second horizontal dimension of the deep conductive via.

4. The device of claim 1 further comprising an integrated circuit device at a surface of the substrate.

5. The device of claim 1 , wherein the substrate is substantially free from integrated circuit devices.

6. The device of claim 1 , wherein the TSV and the metal line form a continuous region formed of a same metallic material, with no barrier layer between the TSV and the metal line.

7. The device of claim 1 further comprising a barrier layer between the TSV and the metal line.

8. A device comprising:
a substrate;
an interconnect structure over the substrate, the interconnect structure comprising:
a plurality of metallization layers comprising:
a bottom metallization layer (M 1 );
a first metallization layer (M 2 ) immediately over the M 1 ;
a second metallization layer (M 3 ) immediately over the M 2 ;
a top metallization layer (Mtop) over the M 3 ; and

at least one metal pad formed in each of the M 1 , M 2 , and M 3 ;
a through-substrate via (TSV) extending from the Mtop to a bottom surface of the substrate;
a plurality of deep conductive vias each extending from a top surface of the Mtop through at least a bottom surface of the Mtop to a respective one of the metal pads, wherein the deep conductive via is a structure different from a structure of the metal pad;
a metal line overlying the interconnect structure and interconnecting the TSV and the deep conductive via; and
a passivation layer overlying the metal line, wherein no portion of a surface of the metal line facing away from the substrate is free from the passivation layer.

9. The device of claim 8 , wherein the substrate is a silicon substrate.

10. The device of claim 8 , wherein the substrate is a dielectric substrate.

11. The device of claim 8 , wherein the TSV and the metal line are formed of a same metallic material, with no diffusion barrier layer between the TSV and the metal line.

12. The device of claim 8 further comprising a diffusion barrier layer between the TSV and the metal line.

13. The device of claim 8 , wherein a ratio of a first horizontal dimension of the TSV to a second horizontal dimension of the deep conductive via is greater than about 1.2.

14. A device comprising:
a substrate;
a plurality of dielectric layers over the substrate;
a plurality of metallization layers formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers lower than the top level of the plurality of metallization layers and higher than the bottom level of the plurality of metallization layers comprises a metal pad;
a deep conductive via extending from the top level of the plurality of dielectric layers and landing on the metal pad, wherein the deep conductive is a structure different from the structure of the metal pad, and wherein a width of the deep conductive via is smaller than a width of the metal pad;
a metal line over the top level of the plurality of dielectric layers and configured to interconnect the deep conductive via to a through-substrate via TSV; and
a passivation layer fully covering the metal line.

15. The device of claim 14 , a barrier layer between the deep conductive via and the metal line.

16. The device of claim 14 , further comprising a through-substrate via (TSV) extending from the top level of the plurality of the dielectric layers to a bottom surface of the substrate.

17. The device of claim 16 , a barrier layer between the TSV and the metal line.

18. The device of claim 1 , wherein the metal pad has a width greater than a width of the deep conductive via.

Assignees

• Lin Jing-Cheng
• Yang Ku-Feng
• Taiwan Semiconductor Mfg

Inventors

• Lin Jing-Cheng
• Yang Ku-Feng

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title