Sinker with a reduced width

Patent metadata

Field	Value
Publication number	US-9293357-B2
Application number	US-201213540542-A
Country	US
Kind code	B2
Filing date	Jul 2, 2012
Priority date	Jul 2, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.

First claim

What is claimed is:

1. A semiconductor structure comprising:
devices;
a semiconductor material having a top surface; and
a sinker providing lateral isolation for the devices, the sinker including:
a first doped region that touches the top surface, a second doped region that touches the first doped region and extends to the top surface, and a plurality of trenches that each extend from the top surface down into the semiconductor material, the first doped region having a first conductivity type, the plurality of trenches being spaced apart from each other, having substantially equal depths, and including a first trench and a second trench; and
a plurality of isolation structures that lie in the plurality of trenches, the plurality of isolation structures being spaced apart and including a first isolation structure and a second isolation structure, the first isolation structure having a non-conductive surface that touches the semiconductor material exposed by the first trench, the second isolation structure having a non-conductive surface that touches the semiconductor material exposed by the second trench, the first doped region lying in between and touching the first isolation structure and the second isolation structure, no region of a second conductivity type lying horizontally in between the first isolation structure and the second isolation structure;
wherein the first doped region includes a horizontal portion that touches the top surface of the semiconductor material, extends to a depth less than a depth of the first and second isolation structures, and extends continuously from the first isolation structure to the second isolation structure, the horizontal portion having a substantially uniform dopant concentration.

2. The semiconductor structure of claim 1 wherein a dopant concentration of the first doped region is substantially greater than a dopant concentration of the second doped region.

3. The semiconductor structure of claim 2 wherein:
the non-conductive surface of the first isolation structure includes a first interior side wall surface, a first exterior side wall surface, and a first bottom surface that connects the first interior side wall surface to the first exterior side wall surface; and
the non-conductive surface of the second isolation structure includes a second interior side wall surface, a second exterior side wall surface, and a second bottom surface that connects the second interior side wall surface to the second exterior side wall surface.

4. The semiconductor structure of claim 3 wherein the first doped region touches the first exterior side wall surface and extends continuously from the first exterior side wall surface to touch the second exterior side wall surface.

5. The semiconductor structure of claim 4 wherein:
a portion of the first doped region extends around the first bottom surface and partially up the first interior side wall surface; and
a portion of the first doped region extends around the second bottom surface and partially up the second interior side wall surface.

6. The semiconductor structure of claim 5 wherein:
a portion of the second doped region lies vertically in between the top surface and the first doped region along the first interior side wall surface; and
a portion of the second doped region lies vertically in between the top surface and the first doped region along the second interior side wall surface.

7. The semiconductor structure of claim 5 and further comprising a well of the first conductivity type that touches the first interior side wall surface and the second doped region.

8. The semiconductor structure of claim 2 wherein:
the semiconductor material has a bottom surface; and
the first doped region is vertically spaced apart from the bottom surface of the semiconductor material.

9. The semiconductor structure of claim 2 wherein the first isolation structure includes a polysilicon core and a non-conductive outer structure that touches a side wall surface and a bottom surface of the polysilicon core to electrically isolate the second doped region from the polysilicon core.

10. The semiconductor structure of claim 2 and further comprising:
a non-conductive layer that touches the top surface of the semiconductor material; and
a metallic contact that extends through the non-conductive layer to make an electrical connection with the first doped region.

11. A semiconductor structure comprising:
a semiconductor body having a top surface; and
a sinker including:
a first isolation trench extending from the top surface into the semiconductor body;
a second isolation trench extending from the top surface into the semiconductor body;
a first doped region of a first conductivity type extending between and touching the first isolation trench and the second isolation trench, the first doped region extending around a bottom of the first isolation trench and partially up an opposite side and extending around a bottom of the second isolation trench and partially up an opposite side;
wherein:
the first doped region includes a horizontal portion that touches the top surface of the semiconductor material, extends to a depth less than a depth of the first and second isolation trenches, and extends continuously from the first isolation trench to the second isolation trench, the horizontal portion having a substantially uniform dopant concentration; and
no region of a second conductivity type extends between the first and second isolation trenches.

12. The semiconductor structure of claim 11 , further comprising a non-conductive structure touching the top surface of the semiconductor body including touching and extending over the horizontal portion of the first doped region.

13. The semiconductor structure of claim 11 , wherein the first isolation trench and the second isolation trench each include a non-conductive outer surface and a polysilicon core.

14. A semiconductor structure comprising:
a semiconductor body having a top surface; and
a sinker including:
a first isolation trench extending from the top surface into the semiconductor body;
a second isolation trench extending from the top surface into the semiconductor body;
a first doped region of a first conductivity type extending between and touching the first isolation trench and the second isolation trench, the first doped region extending around a bottom of the first isolation trench and partially up an opposite side and extending around a bottom of the second isolation trench and partially up an opposite side;
wherein:
the first doped region extends beyond the first isolation trench a distance of approximately 1.5 microns;
the first doped region extends beyond the second isolation trench a distance of approximately 1.5 microns; and
no region of a second conductivity type extends between the first and second isolation trenches.

15. The semiconductor structure of claim 14 , further comprising a non-conductive structure touching the top surface of the semiconductor body including touching and extending over the first doped region.

16. The semiconductor structure of claim 14 , wherein the first isolation trench and the second isolation trench each include a non-conductive outer surface and a polysilicon core.

17. The semiconductor structure of claim 14 , wherein the first doped region includes a horizontal portion that touches the top surface of the semiconductor material, extends to a depth less than a depth of the first and second isolation trenches, and extends continuously from the first isolation trench to the second is

Assignees

• Hu Binghua
• Pendharkar Sameer
• Mathur Guru
• Tamura Takehito
• Texas Instruments Inc

Inventors

• Hu Binghua
• Pendharkar Sameer
• Mathur Guru
• Tamura Takehito

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10P14/66

  characterised by the type of materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W10/0145 Primary

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title