Resonant clocking for three-dimensional stacked devices

Patent metadata

Field	Value
Publication number	US-9287196-B2
Application number	US-201213730331-A
Country	US
Kind code	B2
Filing date	Dec 28, 2012
Priority date	Dec 28, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit.

First claim

What is claimed is:

1. An apparatus comprising:
a stack including a plurality of integrated circuit die layers including at least a first die layer and an adjacent second die layer, each die layer including an active metal side and an opposite RDL (re-distribution layer); and
a plurality of through silicon vias including a first set of through silicon vias formed through the first die layer and a second set of through silicon vias formed through the second die layer, wherein each of the first set of through silicon vias includes an inductive structure and each of the second set of through silicon vias includes a capacitive structure;
wherein the apparatus includes a plurality of resonant circuits to carry clock signals, each of the resonant circuits including a first through silicon via of the first set of through silicon vias used as an inductive circuit element of the resonant circuit and a second through silicon via of the second set of through silicon vias used as a capacitive circuit element of the resonant circuit, the first through silicon via of each resonant circuit being coupled with the respective second through silicon via of the resonant circuit via the RDL of the first die layer;
wherein each of the first set of through silicon vias is utilized both for transport of the clock signals between die layers, including transport of clock signals from the first die layer to the second die layer, and for the generation of inductance for the respective resonant circuit; and
wherein each of the resonant circuits is shared between the first die layer and the second die layer, a clock grid of the first die layer resonating at a same frequency and being synchronous with a clock grid of the second die layer.

2. The apparatus of claim 1 , wherein each resonant circuit includes one or more additional capacitive or inductive circuit elements to tune the frequency of the resonant circuit.

3. The apparatus of claim 1 , further comprising one or more clock drivers to drive a clock signal, the clock signal being driven on the first through silicon via, wherein the resonant circuit is tuned to a frequency of the clock signal.

4. The apparatus of claim 1 , wherein the capacitive structure of the second through silicon via of each resonant circuit including:
a first conductor;
a dielectric layer formed around the first conductor; and
a second conductor formed around the dielectric layer.

5. The apparatus of claim 4 , wherein the first conductor and the second conductor are coaxial conductors.

6. The apparatus of claim 4 , wherein the first conductor has a cylindrical shape and the second conductor has a hollow cylindrical shape.

7. The apparatus of claim 1 , wherein the inductive structure of the first through silicon via of each resonant circuit including:
a conductor;
an insulating layer formed around the conductor; and
a ferromagnetic layer formed around the insulating layer.

8. The apparatus of claim 7 , wherein the conductor has a cylindrical shape and the ferromagnetic layer has a hollow cylindrical shape.

9. A memory device including:
a plurality of die layers including a memory stack of a plurality of memory die layers including at least a first die layer and an adjacent second die layer, each die layer, including an active metal side and an opposite RDL (re-distribution layer), and a system die layer coupled with the memory stack, a plurality of through silicon vias including a first set of through silicon vias formed through the first die layer and a second set of through silicon vias formed through the second die layer; and
a resonant clock network including a plurality of resonant circuits to carry clock signals, each of the resonant circuits including:
a first through silicon via of the first set of through silicon vias, each first through silicon via including an inductive structure, the first through silicon via being used as an inductive circuit element to provide inductance for the resonant circuit, and
a second through silicon via of the second set of through silicon vias, each second through silicon via including a capacitive structure, the second through silicon via being used as a capacitive circuit element of the resonant circuit, the first through silicon via of each resonant circuit being coupled with the respective second through silicon via of the resonant circuit via the RDL of the first die layer;

wherein each of the first set of through silicon vias is utilized both for transport of the clock signals between die layers, including transport of clock signals from the first die layer to the second die layer, and for the generation of inductance for the respective resonant circuit; and
wherein each of the resonant circuits is shared between the first die layer and the second die layer, a clock grid of the first die layer resonating at a same frequency and being synchronous with a clock grid of the second die layer.

10. The memory device of claim 9 , wherein the resonant clock network includes one or more additional capacitive or inductive elements to tune a frequency of the resonant clock network.

11. The memory device of claim 10 , wherein the resonant clock network is tuned to a clock frequency for the memory device.

12. A system comprising:
a processor to process data;
a transmitter or receiver for transmission of data; and
a memory to store data, the memory providing for resonant clocking, the memory including:
a clock driver to provide a clock signal,
a plurality of die layers including a memory stack of a plurality of memory die layers including at least a first die layer and an adjacent second die layer, each die layer, including an active metal side and an opposite RDL (re-distribution layer), and a system die layer coupled with the memory stack, a plurality of through silicon vias including a first set of through silicon vias formed through the first die layer and a second set of through silicon vias formed through the second die layer, and
a resonant clock network including a plurality of LC tank circuits to carry clock signals, each of the LC tank circuits including:
a first through silicon via of the first set of through silicon vias, each first through silicon via including an inductive structure, the first through silicon via being using as an inductive circuit element to provide inductance for the LC tank circuit, and
a second through silicon via of the second set of through silicon vias, each second through silicon via including a capacitive structure, the second through silicon via being used as a capacitive circuit element of the LC tank circuit, the first through silicon via of each LC tank circuit being coupled with the respective second through silicon via of the LC tank circuit via the RDL of the first die layer;

wherein each of the first set of through silicon vias is utilized both for transport of the clock signals between die layers, including transport of clock signals from the first die layer to the second die layer, and for the generation of inductance for the respective LC tank circuit; and
wherein each of the LC tank circuits is shared between the first die layer and the second die layer, a clock grid of the first die layer resonating at a same frequency and being synchronous with a clock grid of the second die layer.

13. The system of claim 12 , wherein the LC tank circuit includes one or more additional capacitive or inductive elements to tune the resonant clocking to the clock frequency.

14. A computer chip comprising:
a first silicon die and a second silicon die, each silicon die including an active metal side and an opposite RDL (re-distribution layer); and

Assignees

• Intel Corp

Inventors

• Saraswat Ruchir
• Zillmann Uwe
• Schaefer Andre
• Lund-Larsen Tor

Classifications

• H10W20/2128

  Coaxial through-semiconductor vias · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W44/243

  for decoupling, e.g. bypass capacitors · CPC title

• H10W44/241

  for passive devices or passive elements · CPC title