Method and structure for determining thermal cycle reliability

Patent metadata

Field	Value
Publication number	US-9287186-B2
Application number	US-12826008-A
Country	US
Kind code	B2
Filing date	May 28, 2008
Priority date	Feb 20, 2004
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

First claim

What is claimed is:

1. A test structure used to determine reliability performance, comprising:
a patterned metallization structure having a plurality of interfaces in a semiconductor structure, which form stress risers, the metallization structure including at least one of:
a via chain formed through layers of patterned metallization in the semiconductor structure such that a plurality of widths of vias are sued to adjust strain in different layers; and
a dummy structure formed to provide a via density in an area of the semiconductor structure to adjust strain in adjacent structures of the test structure; and

a dielectric material surrounding the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exists such that failures occur under given stress conditions to provide a yield indicative of reliability for a manufacturing design.

2. The structure as recited in claim 1 , wherein the same strain value is across a plurality of vias in the test structure.

3. The structure as recited in claim 1 , wherein the patterned metallization structure includes a dual damascene structure.

4. The structure as recited in claim 1 , further comprising conductive liners along bottoms and sidewalls of vias in the dual damascene structure.

5. The structure as recited in claim 4 , wherein the liners include one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) and tungsten (W).

6. The structure as recited in claim 1 , wherein the metallization structure includes one of aluminum (Al), copper (Cu), Gold (Au), silver (Ag) and alloys thereof.

7. The structure as recited in claim 1 , wherein the dielectric material includes an organic material.

8. The structure as recited in claim 1 , wherein the dielectric material includes one of a SiLK (trademark of Dow Chemical) organic dielectric, polyamide, SiCOH, a nitride and an oxide.

9. The structure as recited in claim 1 , wherein the mismatch in CTE between the metallization structure and the dielectric material is greater than about 20 ppm/° C.

10. The structure as recited in claim 1 , wherein the metallization structure includes a stacked via chain having at least two levels of interconnects and vias.

Assignees

• Filippi Ronald Gene
• Gill Jason Paul
• Mcgahay Vincent J
• Mclaughlin Paul Stephen
• Murray Conal Eugene
• Rathore Hazara Singh
• Shaw Thomas M
• Wang Ping-Chuan
• Globalfoundries Inc

Inventors

• Filippi Ronald Gene
• Gill Jason Paul
• Mcgahay Vincent J
• Mclaughlin Paul Stephen
• Murray Conal Eugene
• Rathore Hazara Singh
• Shaw Thomas M
• Wang Ping-Chuan

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• Y10S438/927

  Electromigration resistant metallization · CPC title