Thermal interface material with support structure

Patent metadata

Field	Value
Publication number	US-9263364-B2
Application number	US-201113215416-A
Country	US
Kind code	B2
Filing date	Aug 23, 2011
Priority date	Mar 18, 2009
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.

First claim

What is claimed is:

1. An apparatus, comprising:
a first semiconductor chip having a first footprint;
a second semiconductor chip mounted on the first semiconductor chip and having a second footprint smaller than the first footprint and a side facing away from the first semiconductor chip; and
a thermal interface material layer on the side of the second semiconductor chip, the thermal interface material layer containing a support structure having a third footprint larger than the second footprint.

2. The apparatus of claim 1 , wherein the thermal interface material layer has a first thickness and the support structure has a second thickness less than the first thickness.

3. The apparatus of claim 1 , wherein the thermal interface material layer comprises solder.

4. The apparatus of claim 3 , wherein the solder comprises indium.

5. The apparatus of claim 1 , wherein the support structure comprises a mesh.

6. The apparatus of claim 5 , wherein the mesh comprises a wire mesh.

7. The apparatus of claim 1 , wherein the support structure comprises a plurality of pillars.

8. The apparatus of claim 1 , wherein the first semiconductor chip comprises silicon and plural through-silicon vias.

9. An apparatus, comprising:
a substrate;
a first semiconductor chip mounted to the substrate and having a first footprint;
a second semiconductor chip mounted on the first semiconductor chip and having a second footprint smaller than the first footprint and a side facing away from the first semiconductor chip; and
a thermal interface material layer on the side of the second semiconductor chip, the thermal interface material layer containing a support structure having a third footprint larger than the second footprint.

10. The apparatus of claim 9 , wherein the thermal interface material layer has a first thickness and the support structure has a second thickness less than the first thickness.

11. The apparatus of claim 9 , comprising a heat spreader in thermal contact with the thermal interface material layer.

12. The apparatus of claim 11 , wherein the heat spreader comprises a semiconductor chip package lid.

13. The apparatus of claim 9 , wherein the substrate comprises a circuit board.

14. The apparatus of claim 13 , wherein the circuit board comprises a semiconductor chip package substrate.

15. The apparatus of claim 9 , wherein the support structure comprises a mesh.

16. The apparatus of claim 15 , wherein the mesh comprises a wire mesh.

17. The apparatus of claim 9 , wherein the support structure comprises a plurality of pillars.

18. The apparatus of claim 9 , wherein the first semiconductor chip comprises silicon and plural through-silicon vias electrically connecting the second semiconductor chip to the substrate.

19. The apparatus of claim 9 , wherein the thermal interface material layer comprises solder.

20. The apparatus of claim 19 , wherein the solder comprises indium.

Assignees

• Touzelbaev Maxat
• Refai-Ahmed Gamal
• Yang Yizhang
• Black Bryan
• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Touzelbaev Maxat
• Refai-Ahmed Gamal
• Yang Yizhang
• Black Bryan

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07354

  changes in dispositions · CPC title