Circuits with linear finfet structures
US-9009641-B2 · Apr 14, 2015 · US
Printing minimum width semiconductor features at non-minimum pitch and resulting device
US9263349B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9263349-B2 |
| Application number | US-201314074981-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 8, 2013 |
| Priority date | Nov 8, 2013 |
| Publication date | Feb 16, 2016 |
| Grant date | Feb 16, 2016 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: patterning a first hardmask according to a first shape, a second shape and a dummy shape during a first lithography-etch step in forming of a semiconductor layer, wherein: the first shape and the second shape have a minimum width within the semiconductor layer, a distance between the first shape and the second shape is greater than a minimum pitch, an intervening shape is provided between the first shape and the second shape, the dummy shape is provided within the intervening shape, and the dummy shape is at the minimum pitch from the first shape. 2. The method according to claim 1 , further comprising: designating a second dummy shape within the intervening shape, wherein the second dummy shape is at the minimum pitch from the second shape. 3. The method according to claim 1 , wherein the dummy shape is at the minimum pitch from the second shape. 4. The method according to claim 1 , wherein: the dummy shape has the minimum width. 5. The method according to claim 1 , further comprising: patterning a second hardmask according to the intervening shape during a second lithography-etch step in forming the semiconductor layer. 6. The method according to claim 5 , wherein at least part of the patterned first hardmask and the patterned second hardmask overlap according to the dummy shape. 7. The method according to claim 1 , wherein the semiconductor layer is a metal1 (M1) layer. 8. A method comprising: patterning a first hardmask according to a first shape, a second shape and a dummy shape during a first lithography-etch step in forming a semiconductor layer, wherein: the first shape has a minimum width that is greater than a minimum pitch from the second shape having the minimum width, the dummy shape is provide in an intervening shape between the first shape and the second shape, and the dummy shape is at the minimum pitch from the first shape and the second shape and is at least the minimum width. 9. The method according to claim 8 , wherein: the dummy shape comprises a first portion and a second portion, the first portion being at the minimum pitch from the first shape and the second portion being at the minimum pitch from the second shape. 10. The method according to claim 9 , wherein: the first portion and the second portion each have the minimum width. 11. The method according to claim 8 , further comprising: patterning a second hardmask according to the intervening shape during a second lithography-etch step in forming the semiconductor layer, wherein at least part of the patterned first hardmask and the patterned second hardmask overlap according to the dummy shape.
Assignees
Inventors
Classifications
Elements for improving aerodynamics · CPC title
- G06F30/39Primary
Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title
Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title
using masks for conductive or resistive materials · CPC title
Vias, e.g. via plugs · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9263349B2 cover?
- Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a m…
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F30/39. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 16 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).