System and method for a field-effect transistor with a raised drain structure

Patent metadata

Field	Value
Publication number	US-9257347-B2
Application number	US-201213599642-A
Country	US
Kind code	B2
Filing date	Aug 30, 2012
Priority date	Aug 30, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes forming a frustoconical source by etching a semiconductor substrate, the frustoconical source protruding above a planar surface of the semiconductor substrate; forming a transistor gate, a first portion of the transistor gate surrounding a portion of the frustoconical source and a second portion of the gate configured to couple to a first electrical contact; and forming a drain having a raised portion configured to couple to a second electrical contact and located at a same level above the planar surface of the semiconductor substrate as the second portion of the transistor gate. A semiconductor device having a raised drain structure is also disclosed.

First claim

What is claimed is:

1. A transistor comprising:
a gate having a gate contact surface;
a source region; and
a drain region having first and second drain portions, the first drain portion being surrounded by the gate, the second drain portion being raised and spaced away from the first drain portion and from the gate, the second drain portion having a drain contact surface, wherein the drain contact surface is a topmost surface of the raised second drain portion, the drain contact surface being substantially coplanar with the gate contact surface.

2. The transistor of claim 1 , wherein the source region and the first portion of the drain region are formed on opposite ends of a frustum, the frustum being formed from a semiconducting substrate, wherein the gate surrounds a portion of the frustum such that the gate is electrically coupled with the source region and the first portion of the drain region.

3. The transistor of claim 2 , wherein the drain contact surface is a top surface of a raised platform epitaxially grown from a surface of the semiconducting substrate.

4. The transistor of claim 1 , further comprising a dielectric layer situated between the gate and the source and drain regions, the gate overlapping a portion of the source region and a portion of the first portion of the drain region, the overlapped portion of the source region having a circumference that is smaller than a circumference of the overlapped portion of the drain region.

5. The transistor of claim 1 , further comprising a gate contact coupled with the gate contact surface and a drain contact coupled with the drain contact surface, the gate and drain contacts having a same height.

6. The transistor of claim 4 , wherein the dielectric layer includes an interfacial layer and a high dielectric constant layer.

7. The transistor of claim 5 , wherein the gate contact contacts the gate at an area of the gate that is separated from a surface plane of a semiconducting substrate by a dielectric layer, wherein the dielectric layer is not a gate dielectric layer.

8. A semiconductor device comprising:
an n-type tunneling field-effect transistor (TFET) having a frustoconical protrusion that includes:
a source;
a gate having a gate contact surface and a tunneling control surface, the tunneling control surface surrounding a portion of the frustoconical source; and
a drain having first and second portions, the first portion of the drain being surrounded by the gate, the second portion of the drain being spaced away from the first portion of the drain and from the gate, the second portion of the drain being raised above a surface of a substrate so as to have a top drain contact surface of the raised second portion that is substantially coplanar with the gate contact surface.

9. The semiconductor device of claim 8 , wherein the source of the n-type TFET is doped with p-type dopants and the drain of the n-type TFET is doped with n-type dopants.

10. The semiconductor device of claim 9 , wherein the gate contact surface is parallel to the surface of the substrate, and the tunneling control surface and the portion of the drain are coaxial.

11. A semiconductor device comprising:
an n-type tunneling field-effect transistor (TFET) having a frustoconical protrusion that includes:
a source,
a gate having a gate contact surface and a tunneling control surface, the tunneling control surface surrounding a portion of the frustoconical source, and
a drain, a portion of the drain being raised above a surface of a substrate so as to have a top drain contact surface of the raised portion that is substantially coplanar with the gate contact surface;

a p-type TFET that includes:
an additional source,
an additional gate having an additional gate contact surface; and
an additional drain, a portion of the additional drain being raised above the substrate so as to have a drain contact surface that is substantially coplanar with the additional gate contact surface.

12. The semiconductor device of claim 11 , wherein the additional source of the p-type TFET is doped with n-type dopants and the additional drain of the p-type TFET is doped with p-type dopants.

13. The semiconductor device of claim 11 , further comprising a shallow trench isolation feature between the n-type TFET and the p-type TFET.

14. A field-effect transistor device, comprising:
a conical protrusion, the protrusion protruding above a surface of a substrate;
a gate having a gate contact surface, wherein a tunneling control surface of the gate surrounds a portion of the protrusion;
a drain in a bottom portion of the protrusion, the drain including first and second portions, the first portion being surrounded by the gate, the second portion being spaced apart from the first portion and from the gate, the second portion being raised and having a top drain contact surface that is substantially coplanar with the gate contact surface; and
a source in a top portion of the protrusion.

15. The device of claim 14 , further comprising:
electrical contacts to the gate, the drain, and the source such that a first electrical contact is coupled with the gate contact surface and a second electrical contact is coupled with the drain contact surface, the first and second electrical contacts having a same height.

16. The device of claim 14 , wherein the drain includes a doped portion of the substrate formed through a screening layer parallel to the surface of the substrate.

17. The device of claim 16 , wherein the second portion of the drain is epitaxially grown on the surface of the substrate over the doped portion;
wherein the epitaxially grown second portion is doped with a same type of dopants as used to dope the doped portion.

18. The device of claim 17 , wherein dopants are diffused between the doped portion and the raised portion.

19. The device of claim 14 , wherein the drain in the bottom portion of the conical protrusion further comprises:
dopants diffused through the substrate and the drain such that the dopants extend to a bottom level of the tunneling control surface of the gate, with a portion of the conical protrusion being surrounded by the gate.

20. The device of claim 14 :
wherein the source is doped in the top portion of the conical protrusion,
and the device further including an undoped area of the substrate remaining between the source and the drain.

Assignees

• Chuang Hak-Lay
• Zhu Ming
• Taiwan Semiconductor Mfg

Inventors

• Chuang Hak-Lay
• Zhu Ming

Classifications

• H10D84/0195

  the components including vertical IGFETs · CPC title

• H10D84/0172

  Manufacturing their gate conductors · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title