Methods of singulating substrates to form semiconductor devices using dummy material

US9257342B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9257342-B2
Application numberUS-201414260903-A
CountryUS
Kind codeB2
Filing dateApr 24, 2014
Priority dateApr 20, 2012
Publication dateFeb 9, 2016
Grant dateFeb 9, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a semiconductor device, the method comprising: forming a plurality of active elements in a semiconductor substrate having a first side and an opposite second side, the plurality of active elements being formed adjacent the first side; forming metallization, at the first side, over the plurality of active elements to form a plurality of devices; forming openings in the semiconductor substrate, the openings surrounding each of the plurality of devices; and forming a dummy plug within the openings; providing a tape over the opposite second side of the semiconductor substrate; providing a frame and an adhesive covering the first side of the semiconductor substrate, wherein a portion of the adhesive is disposed within the openings covering the dummy plug; and singulating the semiconductor substrate by removing the frame and the adhesive and followed by removing the dummy plug in the openings from the first side of the semiconductor substrate. 2. The method of claim 1 , wherein the openings comprise a mesh like shape. 3. The method of claim 1 , wherein each of the plurality of devices comprise an integrated circuit. 4. The method of claim 1 , wherein the plurality of active elements comprises transistors. 5. The method of claim 1 , further comprising: thinning the semiconductor substrate to expose the dummy plugs. 6. The method of claim 1 , wherein the dummy plug comprises amorphous carbon. 7. The method of claim 6 , wherein the amorphous carbon comprises tetrahedral amorphous carbon. 8. The method of claim 6 , wherein the amorphous carbon comprises hydrogenated amorphous carbon. 9. The method of claim 1 , wherein the dummy plug comprises carbon and fluorine. 10. The method of claim 1 , wherein the dummy plug comprises nanostructured carbon. 11. The method of claim 1 , wherein the dummy plug comprises polycrystalline carbon. 12. The method of claim 1 , wherein the dummy plug comprises at least 90% carbon. 13. The method of claim 1 , wherein removing the dummy plug comprises using an oxidizing plasma process. 14. The method of claim 1 , wherein the adhesive is removed using a wet etching process and the dummy plug is removed using an oxygen plasma process. 15. A method of forming a semiconductor device, the method comprising: forming openings in a substrate; forming a dummy fill material within the openings; forming an adhesive covering a top surface of the substrate, wherein a portion of the adhesive is disposed within the openings covering the dummy fill material; attaching the substrate to a carrier through the adhesive; thinning the substrate to expose the dummy fill material in the openings; placing a bottom surface of the substrate over a tape; removing the carrier and adhesive after placing the substrate over the tape; and singulating the substrate by removing the dummy fill material in the openings, wherein the dummy fill material is removed after removing the carrier and the adhesive. 16. The method of claim 15 , wherein the substrate comprises a plurality of dies adjacent a front side than an opposite back side. 17. The method of claim 15 , further comprising forming a back side metallization layer after thinning the substrate but before removing the dummy fill material. 18. The method of claim 15 , further comprising forming active regions adjacent a front side of the substrate and forming metallization layer over the active regions. 19. The method of claim 15 , wherein removing the dummy fill material comprises using an oxidizing plasma process. 20. A method of forming a semiconductor device, the method comprising: forming openings in a substrate; forming a dummy fill material within the openings; forming a dummy plug by removing the dummy fill material from over a top surface of the substrate before thinning the substrate; providing a frame and an adhesive covering the top surface of the substrate, wherein a portion of the adhesive is disposed within the openings covering the dummy plug; thinning the substrate to expose the dummy fill material in the openings; placing a tape over a bottom surface of the substrate; and singulating the substrate by removing the frame and the adhesive and followed by removing the dummy fill material in the openings. 21. The method of claim 20 , wherein forming the openings comprises: forming a masking layer over the substrate; forming an etch mask by patterning the masking layer; and etching the substrate using the etch mask. 22. The method of claim 21 , wherein etching the substrate using the etch mask comprising using a oxidizing plasma process.

Assignees

Inventors

Classifications

  • for Group V materials or Group III-V materials · CPC title

  • composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon · CPC title

  • the materials being fluorocarbon compounds, e.g. (CHxFy) n or polytetrafluoroethylene · CPC title

  • formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

  • using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

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Frequently asked questions

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What does patent US9257342B2 cover?
In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 09 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).