Mask treatment for double patterning design

Patent metadata

Field	Value
Publication number	US-9257279-B2
Application number	US-201213434366-A
Country	US
Kind code	B2
Filing date	Mar 29, 2012
Priority date	Mar 29, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first mask layer directly over and contacting an underlying layer;
forming a first pattern in the first mask layer;
after the forming the first pattern in the first mask layer, performing a smoothing process on the first mask layer, the smoothing process rounding corners of the first mask layer in a plan view; and
after completing the smoothing process, patterning the underlying layer using the first mask layer as a mask.

2. The method of claim 1 , wherein the forming the first pattern comprises:
forming a second pattern in a second mask;
transferring the second pattern to the first mask layer;
forming a third pattern in a third mask; and
transferring the third pattern to the first mask layer, the first pattern being a combination of the second pattern and the third pattern.

3. The method of claim 1 , wherein the smoothing process comprises an isotropic dry plasma etch.

4. The method of claim 3 , wherein the isotropic dry plasma etch uses one or more inert gases.

5. The method of claim 3 , wherein the isotropic dry plasma etch comprises an O 2 plasma etch, an N 2 plasma etch, a CO plasma etch, a CO 2 plasma etch, a N 2 /H 2 plasma etch, or argon plasma etch.

6. The method of claim 1 , wherein the smoothing process comprises an isotropic wet etch.

7. The method of claim 1 , wherein the smoothing process comprises depositing a conformal film and performing an anisotropic etch process on the conformal film.

8. A method of forming a semiconductor device, the method comprising:
forming a mask layer on an underlying layer, the mask layer contacting the underlying layer;
forming a first pattern in the mask layer;
forming a second pattern in the mask layer, a combined pattern of the first pattern and the second pattern including one or more corners between sections of the first pattern and sections of the second pattern;
rounding the one or more corners, thereby creating a rounded pattern; and
after completing the rounding, transferring rounded pattern to an underlying layer.

9. The method of claim 8 , wherein the rounding comprises an isotropic dry plasma etch.

10. The method of claim 9 , wherein the isotropic dry plasma etch uses one or more inert gases.

11. The method of claim 8 , wherein the rounding comprises performing an O 2 plasma process, an N 2 plasma process, a CO plasma etch, a CO 2 plasma etch, a N 2 /H 2 plasma etch, or an argon plasma process.

12. The method of claim 8 , wherein the rounding comprises an isotropic wet etch.

13. The method of claim 12 , wherein the isotropic wet etch comprises a dilute hydrofluoric acid.

14. The method of claim 8 , wherein the rounding comprises depositing a conformal film over the combined pattern and anisotropically etching the conformal film after the depositing.

15. A method of forming a semiconductor device, the method comprising:
providing a substrate having an overlying first mask layer, the first mask layer contacting the substrate;
forming a pattern in the first mask layer using a plurality of photolithography exposures, the pattern having one or more sharp corners;
treating the pattern to round the one or more sharp corners, thereby forming a rounded pattern; and
after completing the treating, etching the substrate using the rounded pattern as a mask, the rounded pattern comprising remaining portions of the first mask layer.

16. The method of claim 15 , wherein the treating comprises an isotropic dry plasma etch using an O 2 plasma, an N 2 plasma, a CO plasma etch, a CO 2 plasma etch, a N 2 /H 2 plasma etch, or argon plasma.

17. The method of claim 15 , wherein the treating comprises a wet etch.

18. The method of claim 15 , wherein the treating comprises forming spacers alongside the pattern.

19. The method of claim 15 , wherein the substrate comprises a second mask layer and an underlying material layer, the etching patterning the second mask layer, and further comprising etching the underlying material layer using remaining portions of the second mask layer as a mask.

20. The method of claim 15 , wherein the forming a pattern comprises using a first photolithography and etching process to transfer a first partial pattern to the first mask layer and using a second photolithography and etching process to transfer a second partial pattern to the first mask layer, the one or more sharp corners resulting from an intersection of the first partial pattern and the second partial pattern.

Assignees

• Yang Jiing-Feng
• Chen Chii-Ping
• Chen Dian-Hau
• Taiwan Semiconductor Mfg

Inventors

• Yang Jiing-Feng
• Chen Chii-Ping
• Chen Dian-Hau

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H01L21/31116

  Electricity · mapped topic

• H01L21/0337 Primary

  Electricity · mapped topic