Shielded gate trench MOS with improved source pickup layout

Patent metadata

Field	Value
Publication number	US-9252265-B2
Application number	US-201514660361-A
Country	US
Kind code	B2
Filing date	Mar 17, 2015
Priority date	Mar 11, 2010
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor layer;
a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in a first active area and a second active area, gate runner/termination trenches and a source pickup trench located in a termination area between the first and second active areas, wherein a first conductive region is located at a bottom portion of the active gate, gate runner/termination and source pickup trenches and a second conductive region is located at a top portion of the active gate and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region in the active gate and gate runner/termination trenches; and
a source metal extending from the first active area through the termination area to the second active area, wherein the source metal is connected through a source contact to the first conductive region of the source pickup trench located in the termination area between the first and second active areas.

2. The semiconductor device of claim 1 wherein a gate metal electrically connected to the second conductive regions.

3. The semiconductor device of claim 1 , wherein the source pickup trench is surrounded by adjacent gate runner/termination trenches.

4. The semiconductor device of claim 1 wherein the gate runner/termination trench is asymmetrical, wherein an insulator on a first sidewall of the gate runner/termination trench is thicker than an insulator on a second sidewall of the gate runner/termination trench, the first sidewall being closer to the termination area than the second sidewall.

5. The semiconductor device of claim 1 wherein the gate runner/termination trenches are wider than the active area trenches and the source pickup trenches.

6. The semiconductor device of claim 1 wherein the top of the first conductive region is etched back deeply throughout the device and the source contact is a deep contact to the first conductive region.

7. The semiconductor device of claim 1 further comprising a gate pickup trench extending from the gate runner/termination trenches, wherein the oxide around the second conductive region in the gate pickup trench is thicker than the oxide at the bottom of the gate pickup trench.

8. The semiconductor device of claim 1 wherein an insulator around the second conductive region in the gate pickup trench is thicker than an insulator at the bottom of the gate pickup trench.

9. The semiconductor device of claim 1 , wherein the source pickup trench is surrounded by adjacent gate runner/termination trenches.

10. The semiconductor device of claim 1 , wherein the gate runner/termination trenches include a trench that encloses the first and second active areas and the source pick up trench.

11. A semiconductor device comprising:
a semiconductor layer;
a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trench located in a first termination area and gate runner/termination trench and gate pickup trenches located in a second termination area separated from the first termination area by the active area wherein a first conductive region is located at a bottom portion of the active gate, gate runner/termination, gate pickup and source pickup trenches and a second conductive region is located at a top portion of the active gate, gate pickup and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region;
a gate pickup contact connected to the second conductive regions of the gate pick up trenches located in the second termination area;
a source pickup contact connected to the first conductive region of the source pickup trenches located in the first termination area, wherein the source pickup contact connects to a source metal extending from the active area to the first termination area.

12. The semiconductor device of claim 11 wherein the gate runner/termination trench is asymmetrical, wherein an insulator on a first sidewall of the gate runner/termination trench is thicker than an insulator on a second sidewall of the gate runner/termination trench, the first sidewall being closer to the termination area than the second sidewall.

13. The semiconductor device of claim 11 wherein the gate runner/termination trenches are wider than the active area trenches and the source pickup trenches.

14. The semiconductor device of claim 11 wherein the top of the first conductive region is etched back deeply throughout the device and the source pickup contact is a deep contact to the first conductive region.

15. The semiconductor device of claim 11 wherein an insulator around the second conductive region in the gate pickup trench is thicker than an insulator at the bottom of the gate pickup trench.

16. The semiconductor device of claim 11 , wherein the source pickup trench is surrounded by adjacent gate runner/termination trenches.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Chang Hong
• Su Yi
• Li Wenjun
• Weng Limin
• Chen Gary
• Kim Jongoh
• Chen John

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/663

  the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/517

  characterised by the conducting layers · CPC title