Shielded gate trench MOS with improved source pickup layout

Patent metadata

Field	Value
Publication number	US-8994101-B2
Application number	US-201313865941-A
Country	US
Kind code	B2
Filing date	Apr 18, 2013
Priority date	Mar 11, 2010
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor layer;
a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside the active area wherein a first conductive region is located at a bottom portion of the active gate, gate runner/termination and source pickup trenches and a second conductive region is located at a top portion of the active gate and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region;
a first electrical contact connected to the second conductive regions;
a second electrical contact connected to the first conductive region of the source pickup trenches located in the termination area, wherein the top of the first conductive region is etched back deeply throughout the device and the second electrical contact is a deep contact to the first conductive region; and
a source metal region connected to the second electrical contact and a gate metal region connected to the first electrical contact.

2. The semiconductor device of claim 1 wherein the source pickup trench is located between two adjacent active areas.

3. The semiconductor device of claim 2 , wherein the source pickup trench is surrounded by gate runner/termination trenches.

4. A semiconductor device comprising:
a semiconductor layer;
a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside the active area wherein a first conductive region is located at a bottom portion of the active gate, gate runner/termination and source pickup trenches and a second conductive region is located at a top portion of the active gate and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region;
a first electrical contact connected to the second conductive regions;
a second electrical contact connected to the first conductive region of the source pickup trenches located in the termination area;
a source metal region connected to the second electrical contact and a gate metal region connected to the first electrical contact,
wherein the gate runner/termination trench is asymmetrical, wherein the oxide on a first sidewall of the gate runner/termination trench is thicker than the oxide on the second sidewall of the gate runner/termination trench, the first sidewall being closer to the termination area.

5. The semiconductor device of claim 4 wherein the gate runner/termination trenches are wider than the active gate trenches and the source pickup trenches.

6. A semiconductor device comprising:
a semiconductor layer;
a plurality of trenches formed in the semiconductor layer, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside the active area wherein a first conductive region is located at a bottom portion of the active gate, gate runner/termination and source pickup trenches and a second conductive region is located at a top portion of the active gate and gate runner/termination trenches, and wherein the first and second conductive regions are separated by an intermediate dielectric region;
a first electrical contact connected to the second conductive regions;
a second electrical contact connected to the first conductive region of the source pickup trenches located in the termination area;
a source metal region connected to the second electrical contact and a gate metal region connected to the first electrical contact; and
a gate pickup trench extending from the gate runner/termination trenches, wherein the oxide around the second conductive region in the gate pickup trench is thicker than the oxide at the bottom of the gate pickup trench.

7. The semiconductor device of claim 1 wherein the gate runner/termination trenches are wider than the active gate trenches and the source pickup trenches.

Assignees

• Chang Hong
• Su Yi
• Li Wenjun
• Weng Limin
• Kim Jongoh
• Chen John
• Alpha & Omega Semiconductor

Inventors

• Chang Hong
• Su Yi
• Li Wenjun
• Weng Limin
• Chen Gary
• Kim Jongoh
• Chen John

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/663

  the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/517

  characterised by the conducting layers · CPC title