Conductor structure and method

Patent metadata

Field	Value
Publication number	US-9252156-B2
Application number	US-201514633040-A
Country	US
Kind code	B2
Filing date	Feb 26, 2015
Priority date	Feb 7, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.

First claim

The invention claimed is:

1. A device, comprising:
a circuit including a plurality of active layers;
a stack of semiconductor pads coupled to respective active layers in the plurality of active layers;
the semiconductor pads having outside perimeter lower resistance regions along outside perimeters of the semiconductor pads;
openings in the stack of semiconductor pads, each opening defining an inside perimeter on at least one of the semiconductor pads;
the semiconductor pads having inside perimeter lower resistance regions along the inside perimeters; and
the semiconductor pads having interior regions each including at least one side coupled to the outside perimeter lower resistance region and another side coupled to the inside perimeter lower resistance region, wherein the interior regions have higher resistance relative to the inside perimeter lower resistance regions and the outside perimeter lower resistance regions.

2. The device of claim 1 , each of the outside perimeters including at least one side coupled to a respective active layer in the plurality of active layers.

3. The device of claim 1 , wherein
each of the openings exposing a landing area on a corresponding semiconductor pad, the inside perimeter defined on at least one of the semiconductor pads overlying said corresponding semiconductor pad.

4. The device of claim 3 , wherein the inside perimeter lower resistance regions comprise the landing areas and overlap with the outside perimeter lower resistance regions.

5. The device of claim 3 , wherein said inside perimeter lower resistance regions have implanted impurities that decrease resistivity in said landing areas and said inside perimeter lower resistance regions relative to interior regions of the pads.

6. The device of claim 5 , wherein said implanted impurities are formed by directing the impurities at a substantially normal angle of incidence through said openings and onto the landing areas.

7. The device of claim 3 , including an insulator fill material over the stack of semiconductor pads and the openings, and a plurality of interlayer conductors through the insulator fill material in the openings to contact the landing areas.

8. The device of claim 1 , wherein the outside perimeter lower resistance regions are continuous along opposing sides of the outside perimeters and separated by the interior regions.

9. The device of claim 1 , wherein the semiconductor pads comprise polysilicon relatively lightly doped, or undoped.

10. The device of claim 1 , wherein said outside perimeter lower resistance regions have implanted impurities that decrease resistivity in said outside perimeter lower resistance regions relative to interior regions of the pads.

11. The device of claim 10 , wherein said implanted impurities are formed by directing the impurities at one or more angles of incidence away from the normal around the outside perimeters.

12. The device of claim 1 , wherein an active layer in the plurality of active layers comprises a plurality of strips of active material in contact with one of the semiconductor pads in the stack, the strips of active material comprising components of memory cells.

13. The device of claim 12 , wherein the plurality of strips of active material comprises local bit lines for memory cells in said circuit.

14. The device of claim 12 , wherein the plurality of strips of active material comprises local word lines for memory cells in said circuit.

15. An integrated circuit memory device, comprising:
an array of memory cells, including a plurality of active layers, active layers in the plurality comprising a plurality of patterned layers of semiconductor material, the patterned layers including parallel strips of semiconductor material connected on their ends to a semiconductor pad, the semiconductor pad having an outside perimeter with one side connected to the parallel strips;
the semiconductor pads in the plurality of patterned layers being disposed in a stack;
the semiconductor pads having outside perimeter lower resistance regions along the outside perimeters;
openings in the semiconductor pads, each opening defining an inside perimeter on at least one of the semiconductor pads;
the semiconductor pads having inside perimeter lower resistance regions along the inside perimeters; and
the semiconductor pads having interior regions each including at least one side coupled to the outside perimeter lower resistance region and another side coupled to the inside perimeter lower resistance region, wherein the interior regions have higher resistance relative to the inside perimeter lower resistance regions and the outside perimeter lower resistance regions.

16. The device of claim 15 , wherein each of the openings exposing a landing area on a corresponding semiconductor pad, the inside perimeter defined on at least one of the semiconductor pads overlying said corresponding semiconductor pad.

17. The device of claim 16 , wherein the inside perimeter lower resistance regions comprise the landing areas and overlap with the outside perimeter lower resistance regions.

18. The device of claim 15 , wherein the outside perimeter lower resistance regions are continuous along opposing sides of the outside perimeters and separated by the interior regions.

19. The device of claim 15 , wherein the parallel strips comprise local bit lines for memory cells in said circuit.

20. The device of claim 15 , wherein the parallel strips comprise local word lines for memory cells in said circuit.

Assignees

• Macronix Int Co Ltd

Inventors

• Shih Yen-Hao
• Hsiao Yi-Hsuan
• Chen Chih-Ping

Classifications

• H01L27/11573

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11551

  Electricity · mapped topic

• H10B43/40 Primary

  characterised by the peripheral circuit region · CPC title