Reconfigurable circuit with suspension control circuit

Patent metadata

Field	Value
Publication number	US-9251117-B2
Application number	US-72332010-A
Country	US
Kind code	B2
Filing date	Mar 12, 2010
Priority date	Apr 3, 2009
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.

First claim

What is claimed is:

1. A reconfigurable circuit comprising:
a reconfigurable arithmetic execution unit array comprising:
a plurality of arithmetic execution units, and
a network circuit configured to provide reconfigurable connections between the arithmetic execution units;

a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array; and
a buffer circuit comprising:
a counter configured to output a count value;
a temporary storage unit; and
a selector configured to:
supply the reconfigurable arithmetic execution unit array with a first data from an external buffer in response to the count value being equal to zero; and
supply the reconfigurable arithmetic execution unit array with a second data from the temporary storage unit in response to the count value being equal to one or larger than one.

2. The reconfigurable circuit of claim 1 , further comprising an access request disabling circuit configured to disable a data access request from the reconfigurable arithmetic execution unit array to the external buffer upon suspension of the operation of the reconfigurable arithmetic execution unit array.

3. The reconfigurable circuit of claim 2 , wherein the buffer circuit comprises:
a number specifying register configured to store data indicative of a number; and
a shift register configured to store N data items supplied from the external buffer from a moment at which the operation of the reconfigurable arithmetic execution unit array is suspended, N being an integer equal to the number indicated by the data stored in the number specifying register.

4. The reconfigurable circuit of in claim 1 , wherein the counter is configured to:
count up the count value in response to a first clock signal that is synchronized with a shift operation of the shift register during a suspended period of the operation of the reconfigurable arithmetic execution unit array;
maintain the count value at a current value in the absence of the shift operation of the shift register during the suspended period of the operation of the reconfigurable arithmetic execution unit array; and
count down the count value in response to a second clock signal in the absence of the shift operation of the shift register during an operating period of the reconfigurable arithmetic execution unit array.

5. The reconfigurable circuit of claim 1 , wherein the suspension control circuit is configured to suspend the operation of the reconfigurable arithmetic execution unit array in response to at least one of a stall request from the reconfigurable arithmetic execution unit array and a stall request from the external buffer.

6. The reconfigurable circuit of claim 1 , wherein the buffer circuit comprises:
a first buffer circuit configured to:
temporarily store a third data supplied from a first external buffer upon suspension of the operation of the reconfigurable arithmetic execution unit array, and
supply the third data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array; and

a second buffer circuit configured to:
temporarily store a fourth data supplied from a second external buffer upon suspension of the operation of the reconfigurable arithmetic execution unit array; and
supply the fourth data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.

7. The reconfigurable circuit of claim 1 , wherein the first data or the second data comprises:
data having a valid value or an invalid value; and
valid-state indicating data that indicates whether the data that assumes either a valid value or an invalid value is a valid value or an invalid value.

8. A reconfigurable circuit system comprising:
a reconfigurable circuit; and
an external buffer for which the reconfigurable circuit performs a data read operation and a data write operation,
wherein the reconfigurable circuit comprises:
a reconfigurable arithmetic execution unit array including:
a plurality of arithmetic execution units, and
a network circuit configured to provide reconfigurable connections between the arithmetic execution units;

a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array; and
a buffer circuit comprising:
a counter configured to output a count value;
a temporary storage unit; and
a selector configured to:
supply the reconfigurable arithmetic execution unit array with a first data from an external buffer in response to the count value being equal to zero; and
supply the reconfigurable arithmetic execution unit array with a second data from the temporary storage unit in response to the count value being equal to one or larger than one.

9. The reconfigurable circuit system of claim 8 , further comprising an access request disabling circuit configured to disable a data access request from the reconfigurable arithmetic execution unit array to the external buffer upon suspension of the operation of the reconfigurable arithmetic execution unit array.

10. The reconfigurable circuit system of claim 9 , wherein the buffer circuit comprises:
a number specifying register configured to store data indicative of a number; and
a shift register configured to store N data items supplied from the external buffer from a moment at which the operation of the reconfigurable arithmetic execution unit array is suspended, N being an integer equal to the number indicated by the data stored in the number specifying register.

11. The reconfigurable circuit system of claim 10 , wherein the counter is configured to:
count up the count value in response to a first clock signal that is synchronized with a shift operation of the shift register during a suspended period of the operation of the reconfigurable arithmetic execution unit array;
maintain the count value at a current value in the absence of the shift operation of the shift register during the suspended period of the operation of the reconfigurable arithmetic execution unit array; and
count down the count value in response to a second clock signal in the absence of the shift operation of the shift register during an operating period of the reconfigurable arithmetic execution unit array.

12. The reconfigurable circuit system of claim 8 , wherein the suspension control circuit is configured to suspend the operation of the reconfigurable arithmetic execution unit array in response to at least one of a stall request from the reconfigurable arithmetic execution unit array and a stall request from the external buffer.

13. The reconfigurable circuit system of claim 8 , wherein the buffer circuit comprises:
a first buffer circuit configured to:
temporarily store a third data supplied from a first external buffer upon suspension of the operation of the reconfigurable arithmetic execution unit array, and
supply the third data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array; and

a second buffer circuit configured to:
temporarily store a fourth data supplied from a second external buffer upon suspension of the operation of the reconfigurable arithmetic execution unit array; and

supply the fourth data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.

14. The reconfigurable circuit system of claim 8 , wher

Assignees

• Hanai Takashi
• Sutou Shinichi
• Cypress Semiconductor Corp

Inventors

• Hanai Takashi
• Sutou Shinichi

Classifications

• G06F9/3897

  with adaptable data path · CPC title

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title