Apparatus and method for compressing trace data

Patent metadata

Field	Value
Publication number	US-9152422-B2
Application number	US-201113177823-A
Country	US
Kind code	B2
Filing date	Jul 7, 2011
Priority date	Jan 18, 2011
Publication date	Oct 6, 2015
Grant date	Oct 6, 2015

Abstract

An apparatus and method for compressing trace data is provided. The apparatus includes a detection unit configured to detect trace data corresponding to one or more function units performing a substantially significant operation in a reconfigurable processor as valid trace data, and a compression unit configured to compress the valid trace data.

First claim

What is claimed is:

1. A method of compressing trace data, comprising:
detecting trace data corresponding to one or more function units performing an instruction in a reconfigurable processor as valid trace data, to exclude at least one of a no-operation (NOP) instruction and a predicate instruction for pipelining; and
compressing the valid trace data for each configuration information without compressing the configuration information, wherein the detecting and the compressing each is performed by a processor,
wherein the trace data comprises memory access information corresponding to each of the function units, and corresponding to configuration information related to the processor, excluding the data accessed using the memory access information, and
wherein the configuration information defines instructions allocated to the function units and connections between the function units, and
wherein the compressing the valid trace data comprises generating additional information corresponding to a detection of the valid trace data and generating compressed trace data by compressing both the valid trace data and the additional information.

2. The method of claim 1 , wherein the detecting the valid trace data comprises identifying one or more function units to which a NOP instruction is mapped and detecting all the trace data, except for trace data corresponding to the identified function units, as the trace data corresponding to the one or more function units performing the instruction.

3. The method of claim 1 , wherein the detecting the valid trace data comprises identifying one or more function units to which a predicate instruction for pipelining is mapped and detecting all the trace data, except for trace data corresponding to the identified function units, as the trace data corresponding to the one or more function units performing the instruction.

4. The method of claim 3 , wherein the predicate instruction is an instruction with no specific function used in one of a prologue stage before a kernel stage of the pipelining and an epilogue stage after the kernel stage of the pipelining.

5. The method of claim 1 , wherein the detecting the valid trace data comprises identifying the one or more function units performing the instruction based on schedule information provided by a compiler of the reconfigurable processor and detecting trace data corresponding to the identified function units as the valid trace data.

6. An apparatus having a processor for compressing trace data, comprising:
one or more function units performing any of a no-operation instruction, a predicate instruction, and another instruction;
a detector configured to detect trace data corresponding to the one or more function units performing the other instruction in a reconfigurable processor as valid trace data; and
a compressor configured to compress the valid trace data for each configuration information without compressing the configuration information, wherein the detector is configured to exclude trace data corresponding to the one or more function units performing the no-operation instruction and the predicate instruction,
wherein the trace data comprises memory access information corresponding to each of the function units and corresponding to configuration information related to the processor, excluding the data accessed using the memory access information, and
wherein the configuration information defines instructions allocated to the function units and connections between the function units, and
wherein the compressor is further configured to generate additional information corresponding to a detection of the valid trace data and to generate compressed trace data by compressing both the valid trace data and the additional information.

7. A method of compressing trace data, comprising:
performing any of a no-operation instruction, a predicate instruction, and another instruction by one or more function units;
detecting trace data corresponding to the one or more function units performing the other instruction in a reconfigurable processor as valid trace data; and
compressing the valid trace data for each configuration information without compressing the configuration information, wherein:
the detecting excludes trace data corresponding to the one or more function units performing the no-operation instruction and the predicate instruction; and
the detecting and the compressing each is performed by a processor,
wherein the trace data comprises memory access information corresponding to each of the function units and corresponding to configuration information related to the processor, excluding the data accessed using the memory access information, and
wherein the configuration information defines instructions allocated to the function units and connections between the function units, and
wherein the compressing the valid trace data comprises generating additional information corresponding to a detection of the valid trace data and generating, compressed trace data by compressing both the valid trace data and the additional information.

8. An apparatus having a processor for compressing trace data, comprising:
a detector configured to detect trace data corresponding to one or more function units performing an instruction in a reconfigurable processor as valid trace data, to exclude at least one of a no-operation (NOP) instruction and a predicate instruction for pipelining; and
a compressor configured to compress the valid trace data for each configuration information without compressing the configuration information,
wherein the trace data comprises memory access information corresponding to each of the function units and corresponding to configuration information related to the processor, excluding the data accessed using the memory access information, and
wherein the configuration information defines instructions allocated to the function units and connections between the function units, and
wherein the compressor is further configured to generate additional information corresponding to a detection of the valid trace data and to generate compressed trace data by compressing both the valid trace data and the additional information.

9. The apparatus of claim 8 , wherein the detector is further configured to identify one or more function units to which a NOP instruction is mapped and detect all the trace data, except for trace data corresponding to the identified function units, as the trace data corresponding to the one or more function units performing the instruction.

10. The apparatus of claim 8 , wherein the detector is further configured to identify one or more function units to which a predicate instruction for pipelining is mapped and detect all the trace data, except for trace data corresponding to the identified function units, as the trace data corresponding to the one or more function units performing the instruction.

11. The apparatus of claim 8 , wherein the additional information comprises at least one of a count value of a program counter of the reconfigurable processor, identification information corresponding to one or more function units currently operating, identification information corresponding to other function units currently not operating, schedule information provided by a compiler of the reconfigurable processor, and compression type information.

12. The apparatus of claim 8 , wherein the detector and the compressor each is implemented by the processor.

13. The apparatus of claim 8 , wherein the generated additional information indicates which of the function units perform an operation to exclude at least one of a no-operation (NOP) instructi

Assignees

• Kim Jae-Young
• Yoo Dong-Hoon
• Cho Yeon-Gon
• Shim Hee-Jun
• Kim Chang-Moo
• Samsung Electronics Co Ltd

Inventors

• Kim Jae-Young
• Yoo Dong-Hoon
• Cho Yeon-Gon
• Shim Hee-Jun
• Kim Chang-Moo

Classifications

• G06F9/30072

  to perform conditional operations, e.g. using predicates or guards · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F11/3636 Primary

  by tracing the execution of the program · CPC title

• G06F9/30189 Primary

  according to execution mode, e.g. mode flag · CPC title