Carrier substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9247654-B2
Application number	US-201313966295-A
Country	US
Kind code	B2
Filing date	Aug 14, 2013
Priority date	May 7, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings. The first openings expose the first circuit layer and an aperture of each first opening is increased gradually from the third surface to the fourth surface. The conductive blocks fill the first openings and connect with the first circuit layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

First claim

What is claimed is:

1. A carrier substrate, comprising:
a dielectric layer having a first surface and a second surface opposite to each other and a plurality of blind vias;
a first circuit layer embedded in the first surface of the dielectric layer and having an upper surface and a lower surface opposite to each other, the upper surface exposed from the first surface of the dielectric layer, wherein the blind vias extend from the second surface to the first circuit layer and expose a portion of the lower surface of the first circuit layer;
an insulation layer having a third surface and a fourth surface opposite to each other and disposed on the first surface of the dielectric layer through the fourth surface and covers a portion of the upper surface of the first circuit layer, the insulation layer having a plurality of first openings extending from the third surface to the fourth surface, wherein the first openings expose another portion of the upper surface of the first circuit layer, an aperture of each first opening is increased gradually from the third surface to the fourth surface, and the apertures of the first openings on the fourth surface are greater than a width of the exposed first circuit layer;
a plurality of conductive blocks respectively disposed in the first openings of the insulation layer and connected with another portion of the upper surface of the first circuit layer exposed by the first openings; and
a first conductive structure disposed on the second surface of the dielectric layer and comprising a plurality of conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

2. The carrier substrate as recited in claim 1 , further comprising:
a built-up structure disposed on the second surface of the second circuit layer and the dielectric layer, the built-up structure comprising at least one built-up dielectric layer and a second conductive structure disposed on the built-up dielectric layer, wherein the second conductive structure at least comprises a plurality of second conductive vias disposed in the built-up dielectric layer and a built-up circuit layer disposed on a portion of the built-up dielectric layer, and a portion of the second conductive vias connect with the second circuit layer.

3. The carrier substrate as recited in claim 1 , further comprising a plurality of conductive bumps disposed corresponding to the first openings of the insulation layer and respectively connecting with the conductive blocks.

4. The carrier substrate as recited in claim 1 , further comprising:
a plurality of conductive towers respectively disposed on the conductive blocks, wherein each conductive tower has a tip face and a base face opposite to each other and a diameter of each conductive tower is increased gradually from the tip face to the base face.

Assignees

• Unimicron Technology Corp

Inventors

• Lin Chun-Ting

Classifications

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K3/4015 Primary

  using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres · CPC title

• H05K2203/041

  Solder preforms in the shape of solder balls · CPC title

• H05K3/0097

  Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards (H05K3/0052 takes precedence) · CPC title

• H05K2201/09827

  Tapered, e.g. tapered hole, via or groove · CPC title