Strained structures of semiconductor devices

Patent metadata

Field	Value
Publication number	US-9246004-B2
Application number	US-201113296723-A
Country	US
Kind code	B2
Filing date	Nov 15, 2011
Priority date	Nov 15, 2011
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A strained structure of a semiconductor device is disclosed. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a gate stack on the major surface of the substrate; a shallow trench isolation (STI) disposed on one side of the gate stack, wherein the STI is within the substrate; and a cavity filled with a strained structure distributed between the gate stack and the STI, wherein the cavity comprises one sidewall formed by the STI, one sidewall formed by the substrate, and a bottom surface formed by the substrate, wherein the strained structure comprises a SiGe layer and a first strained film adjoining the sidewall of the STI.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a major surface;
a gate stack on the major surface of the substrate;
a shallow trench isolation (STI) disposed on one side of the gate stack, wherein the STI is within the substrate; and
a cavity filled with a strained structure distributed between the gate stack and the STI, wherein the cavity comprises one sidewall formed by the STI, one sidewall formed by the substrate, and a bottom surface formed by the substrate, wherein the strained structure comprises a SiGe layer and a first strained film, the first strained film separates the SiGe layer from the STI, the SiGe layer extends over a top surface of the first strained film, and the first strained film comprises II-VI semiconductor material or III-V semiconductor material.

2. The semiconductor device of claim 1 , wherein a width of the first strained film is less than a width of the SiGe layer.

3. The semiconductor device of claim 1 , wherein a ratio of a width of the SiGe layer to a width of the first strained film is from 5 to 100.

4. The semiconductor device of claim 1 , wherein a thickness of the first strained film is less than a thickness of the SiGe layer.

5. The semiconductor device of claim 1 , wherein a thickness of the first strained film is less than a thickness of the SiGe layer.

6. The semiconductor device of claim 1 , wherein a ratio of a thickness of the first strained film to a thickness of the SiGe layer is from 0.8 to less than 1.0.

7. The semiconductor device of claim 1 , wherein the first strained film comprises a II-VI semiconductor material selected from the group consisting of ZnSe, ZnO, CdTe, and ZnS.

8. The semiconductor device of claim 1 , wherein the first strained film comprises a III-V semiconductor material selected from the group consisting of GaAs, InAs, InGaAs, AlAs, AlGaAs, InP, AlInP, InGaP, GaN, AlGaN, InN, InGaN, InSb, InGaAsSb, InGaAsN, and InGaAsP.

9. The semiconductor device of claim 1 , further comprising a dummy gate stack with a sidewall spacer over the STI, wherein at least a portion of the first strained film is below the sidewall spacer.

10. The semiconductor device of claim 1 , wherein the strained structure further comprises a second strained film on the sidewall of the substrate.

11. The semiconductor device of claim 10 , wherein a width of the second strained film is substantially equal to a width of the first strained film.

12. The semiconductor device of claim 10 , a width of the second strained film is less than a width of the SiGe layer.

13. The semiconductor device of claim 10 , wherein the second strained film comprises II-VI semiconductor material or III-V semiconductor material.

14. A semiconductor device comprising:
a substrate comprising a major surface;
a first gate stack on the major surface of the substrate;
a shallow trench isolation (STI) within the substrate, wherein the STI is on one side of the first gate stack;
a second gate stack on the STI; and
a strained structure in the substrate between the first gate stack and the STI, wherein the strained structure comprises:
a strained film in direct contact with the STI, wherein the strained film is under at least a portion of the second gate stack, and the strained film comprises a II-VI semiconductor material or a III-V semiconductor material, and
a SiGe layer, wherein a first sidewall of the SiGe layer is in direct contact with the strained film, and a bottom of the SiGe layer contacts the substrate.

15. The semiconductor device of claim 14 , wherein a second sidewall of the SiGe layer is in direct contact with the substrate, and the second sidewall is opposite to the first sidewall.

16. The semiconductor device of claim 14 , wherein a second sidewall of the SiGe layer is aligned with a side of the second gate stack, and the second sidewall is opposite to the first sidewall.

17. The semiconductor device of claim 14 , wherein the SiGe film is thicker than the strained film.

18. A semiconductor device comprising:
a substrate comprising a major surface;
a first gate stack on the major surface of the substrate;
a shallow trench isolation (STI) within the substrate, wherein the STI is on one side of the gate stack;
a second gate stack over the STI, wherein the STI comprises an upper portion and a lower portion, a width of the lower portion is greater than a width of the upper portion, and a sidewall of the upper portion of the STI is recessed with respect to a sidewall of the second gate stack; and
a strained structure in the substrate between the first gate stack and the STI, wherein the strained structure comprises:
a strained film in direct contact with the sidewall of the upper portion of the STI, and
a SiGe layer, wherein a first sidewall of the SiGe layer is in direct contact with the strained film.

19. The semiconductor device of claim 18 , wherein a second sidewall of the SiGe layer is in direct contact with the substrate, a bottom of the SiGe layer is in direct contact with the substrate, and the second sidewall of the SiGe layer is opposite the first sidewall of the SiGe layer.

20. The semiconductor device of claim 1 , wherein a width of a top portion of the STI is different from a width of a bottom portion of the STI.

Assignees

• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen
• Taiwan Semiconductor Mfg

Inventors

• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10D30/797 Primary

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/0275

  forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions · CPC title

• H10D62/82

  Heterojunctions · CPC title